Blended negative electrodes with a mix of graphite and silicon are attractive solutions to extend the energy density of lithium-ion batteries. Given the huge volume expansion of silicon, the relative lithiation/delithiation of both active materials upon cycling is crucial to determine the mechanical behavior of the electrode. It is complicated however by the potential hysteresis displayed by silicon. We focus on a blended anode with 16 wt% of silicon carbon composite (SiC-C) at a gravimetric capacity of 1500 mAh.g(-1)mixed with 84 wt% graphite. A multi-scale porous electrode model with three different hierarchical units has been developed to account for the morphology of the SiC-C composed of nanoflakes of silicon embedded in a carbon matrix. The developed physics-based model is parametrized with appropriate experiments and validated for two electrodes loadings and various operating conditions. The validated model allows to probe the lithiation competition between the silicon and the carbon within the composite and the graphite. It is able to capture the streaking features revealed by synchrotron experiments. In particular, we show that at higher C-rates, the lithiation of the silicon is delayed and reduced compared to the graphite one. Quantifying this relative competition is valuable as aging effects are significantly accelerated by the expansion of the silicon.

We present for the first time an experimental study of thermal effects in 3D sequential integration, including Self-Heating Effect (SHE) and thermal coupling between the two levels of ultra-thin body FDSOI transistors. We extracted a large set of experimental data using different thermometry techniques, and different heater-sensor configurations allowed by this specific stacked integration. We described SHE in top and bottom transistor levels, as well as the influence of a transistor in ON state on a transistor stacked above or below. At the same time, we provide for the first time an experimental validation that the temperature increase given by gate resistance thermometry technique is equal to the temperature in the channel given by the subthreshold slope. Finally, this work can be also used to manage thermal effects for logic or analog applications, and help further optimization of 3D sequential integrated circuits through both technology and design solutions.

This work investigates the possibility to reduce the Solid Phase Epitaxy Regrowth (SPER) temperature for dopant activation needed in 3D sequential integration. The electrical results obtained on 28nm FDSOI devices show that 500°C SPER can yield similar performance to that of 600°C SPER and 1050°C spike anneal. This paper highlights the advantages of using a <;100>-oriented channel and tilted implantation to successfully reduce the SPER thermal budget. It also confirms that the channel can be used as a seed for the recrystallization. The analysis takes into account the SPER rate dependence on temperature, crystalline orientation, dopant type and dopant concentration.

We have fabricated 3D-monolithic transistors on two tiers. We experimentally evidence the asymmetric double-gate (DG) behavior of a top-tier transistor, resulting in a better ON-state current (I-ON) / OFF-state current (I-OFF) tradeoff than in single-gate (SG) mode. Moreover, a 3D-shared contact between a top and bottom electrode is experimentally demonstrated; paving the way for a local back gate, possibly connected with the top gate by a 3D-shared contact. Assuming such a construct, we have performed extensive layout and spice simulations of standard cells and SRAMs. We evidence that the back-gate overlap on the source and drain must be minimized to mitigate the parasitic capacitances. The best layout configurations of a loaded 1-finger inverter yields a 24% frequency gain at a given static power and V-DD=0.6V supply voltage, compared to SG, or to a static power divided by 5, compared to SG under Forward Body Bias (FBB). These performance boosts may be obtained without any area penalty and assuming a 20nm-thin BOX. Similarly, a 29% improvement of the read and write currents of 6T SRAMs is contemplated at V-DD=0.8V. Such new functionality provided by 3D-monolithic even enables making 4T SRAMs that are fully functional at V-DD=0.8V by improving their retention and, in turn, the maximum number of bitcells per column from 50 (SG) to 300 with a dynamic back-bias.

3D Sequential Integration (3DSI) with ultra-small 3D contact pitch (<;100nm) offers new 3D partitioning options at fine granularities. This paper reviews potential applications ranging from computing to sensor interface and gives an update on 3DSI device development. Low-temperature processing techniques have made great progress and High Performance (HP) digital stacked FETs for computing application can be achieved with a 500°C Thermal Budget (TB). In addition, ULK/metal lines capable of withstanding this TB can be used between stacked tiers. Ultra-Low TB FETs (<;400°C) have potential for low-power applications and allow for the stacking of multiple layers.

The ‘BOX creep’ technique consists in introducing stress in a SOI layer by taking advantage of the creep of the buried oxide enabled its low viscosity at high temperature. In this study, we deeply investigate the impact of the structure geometry and parameters on the efficiency of creep through mechanical simulations. We find that a 1.1GPa stress can be achieved for an active length of 400nm. This result shows that BOX creep can be an efficient way to boost the performance of future FDSOI technology generations.

For the first time, a low temperature (LT) FinFET process is demonstrated, using Solid Phase Epitaxy Regrowth (SPER), gate last integration and Self Aligned Contact (SAC). The LT devices exhibit performances close to those of the High Temperature Process Of Reference (HT POR). Several techniques of SPER doping are investigated and an innovative Double SPER (DSPER) process using two amorphization/recrystallization steps, is demonstrated. This DSPER process has the advantage of doping the bulk of the S/D junctions. This work opens the door to the fabrication of high-performance LT FinFETs for 3D sequential integration.

3D sequential integration motivates the development of low temperature technological modules. Alternatively to classical non-selective annealing techniques, sub-microsecond laser annealing allows high temperature treatment of a sub-micrometer surface region while keeping the underneath structures at much lower temperature. In this contribution, we present recent advances in ultra-violet nanosecond laser annealing targeting monolithic 3D integration. Emphasis will be put on the demonstration of dopant activation in thin implanted SOI structures, simulating source and drain regions. Cu / ULK interconnects stability upon nanosecond laser annealing is also investigated.

The different regimes encountered when submitting ultra-thin SOI structures implanted with arsenic to single pulse laser annealing with increasing energy density, are identified. It is found that nanosecond UV laser annealing can be successfully applied to rebuild a perfect monocrystalline SOI layer and reach arsenic activation levels at least as high as rapid thermal processing, with a reasonably large process window. Thanks to electrical and morphological characterizations, the defective or polycrystalline silicon obtained below the optimum range is evidenced, as well as the loss of monocrystalline nature of the silicon at the upper end of the process window.

We present deep insights on the integration and physics of two new strain boosters for FDSOI CMOS. "STRASS" and "BOX creep" techniques (for tensily and compressively stressed channels, respectively) are for the first time integrated in a localized manner on a state-of-the-art 14nm FDSOI route. STRASS enables to achieve +1.6 GPa in SOI active regions (w.r.t. +1.3 GPa for thin BOX sSOI). BOX creep process leads to more than +10% in hole mobility and +6% in Ieff(Ioff) plots. The BOX creep efficiency is investigated with respect to device dimensions: the electrical data evolution matches the proposed mobility model based on 2D simulated stress profiles.

3D sequential integration enables the full use of the third dimension thanks to its unique contact density far above the possibilities of 3D packaging solutions. However, as the transistors are sequentially stacked over each other, the thermal budget allowed for the fabrication of the top transistor is limited by the maximal temperature accepted by the already made bottom one. It was previously described that a thermal budget of T>500°C is enough to degrade the bottom transistors performance. So the technological challenge is to develop low temperature routines for the fabrication of the top devices. For that, different processes have to be adapted, mainly the dopant activation step, where the T>1000°C spike annealing must be replaced. In this contribution, we present the feasibility to dope by solid phase epitaxial regrowth (SPER) at 450°C thin Si films (22nm) containing high dopant concentration of 5×1020at/cm3. For n- and p-type dopants, the 450°C SPER rendered low sheet resistance values, as low as the ones obtained with the high temperature activation method.

In this work it is shown that laser annealing can be used for electrical activation of phosphorus implanted in extremely thin SOI structures. We characterized crystallinity, surface morphology, dopant diffusion and activation as a function of the laser energy density. It is evidenced that pulsed laser annealing (wavelength: 308 nm and pulse duration: 160 ns) allows the perfect crystal recovery of the implanted silicon layers. An optimum was found for a fluence (0.85 J/cm(2) for the blanket SOI wafers used here) for which a perfect mono-crystalline SOI layer is obtained. Moreover, sheet resistance evolution shows that very high activation rates, comparable to those obtained by rapid thermal processing or solid phase epitaxial regrowth, can be achieved. The impact of multi-pulse (2 or 5 cumulated pulses) annealing as well as the use of shorter pulses (80 ns) is investigated.

In this paper, the recent advances in low temperature process in view of 3D VLSI integration are reviewed. Thanks to the optimization of each low temperature process modules (dopant activation, gate stack, epitaxy, spacer deposition) and silicide stability improvement, the top layer thermal budget fabrication has been decreased in order to satisfy the requirements for 3D VLSI integration.

In this paper, the energy process window of nanosecond (ns) laser annealing for junctions activation has been determined for several dopants (As, P, BF 2 ). The different recrystallization states observed when tuning laser energy density are explained by numerical simulations. Within these conditions, the laser impact on the thermal stability of ULK/copper inter-tiers interconnections has been evaluated for a 28nm node backend metal 1 design rules technology both from morphological and electrical perspectives. This study highlights the interest of ns laser anneal for CoolCube™ 3D integration.

The amorphization by implantation of strained silicon–germanium epitaxial layers is investigated by experiments and simulation according to the germanium content in the film and the implantation conditions. Experimental results are used to calibrate a numerical model based on a combined approach between a Binary Collision Approximation (BCA) module and a kinetic Monte Carlo (kMC) module. The calibration is implemented in the Synopsys Sentaurus Process simulator and a close agreement between simulations and experiments is shown. Experimental results show that by increasing the germanium concentration, amorphous thickness is reduced for high energy implantations. Germanium content seems to have less impact at low energy implantations.

The framework of this paper is the improvement of direct-forcing immersed boundary methods in presence of moving obstacles. In particular, motivations for the use of the Direct Forcing (DF) method can be found in the advantage of a fixed computational mesh for fluid–structure interaction problems. Unfortunately, the direct forcing approach suffers a serious drawback in case of moving obstacles: the well known spurious force oscillations (SFOs). In this paper, we strengthen previous analyses of the origin of the SFO through a rigorous numerical evaluation based on Taylor expansions. We propose a remedy through an easy-to-implement regularization process (regularized DF). Formally, this regularization is related to the blending of the Navier–Stokes solver with the interpolation, but no modification of the numerical scheme is needed. This approach significantly cuts off the SFOs without increasing the computational cost. The accuracy and the space convergence order of the standard DF method are conserved. This is illustrated on numerical and physical validation test cases ranging from the Taylor–Couette problem to a cylinder with an imposed sinusoidal motion subjected to a cross-flow.

3D sequential integration requires top FETs processed with a low thermal budget (500–600°C). In this work, high performance low temperature FDSOI devices are obtained thanks to the adapted extension first architecture and the introduction of mobility boosters (pMOS: SiGe 27% channel / SiGe:B 35% RSD and nMOS: SiC:P RSD). This first demonstration of n and p extension first FDSOI devices shows that low temperature activated device can match the performance of a device with state-of-the-art high temperature process (above 1000°C).

A framework for the simulation of nanosecond laser annealing of structures found in 3D sequential integration is presented. The framework includes a finite difference frequency domain Maxwell solver and a Poisson solver for the thermal diffusion. Simple applications illustrate the advantages, expected difficulties and optimization levers of this annealing technique.

3D VLSI integration is a promising alternative path towards CMOS scalability. It requires Low Temperature (LT) processing (≤600°C) for top FET fabrication. In this work, record performance is demonstrated for LT TriGate and FDSOI devices using Solid Phase Epitaxy (SPE). Optimization guidelines for further performance improvement are given for FD, TriGate and FinFET on insulator with the constraint of 14nm node channel strain preservation. This work concludes that extension first process scheme (implantation before the raised source and drain epitaxy) is required for FDSOI and TriGate architectures.