Real-time coupling of cell cultures to neuromorphic circuits necessitates a neuromorphic network that replicates biological behaviour both on a per-neuron and on a population basis, with a network size comparable to the culture. We present a large neuromorphic system composed of 9 chips, with overall 2880 neurons and 144M conductance-based synapses. As they are realized in a robust switched-capacitor fashion, individual neurons and synapses can be configured to replicate with high fidelity a wide range of biologically realistic behaviour. In contrast to other exploration/heuristics-based approaches, we employ a theory-guided mesoscopic approach to configure the overall network to a range of bursting behaviours, thus replicating the statistics of our targeted in-vitro network. The mesoscopic approach has implications beyond our proposed biohybrid, as it allows a targeted exploration of the behavioural space, which is a non-trivial task especially in large, recurrent networks.

With the discovery of ferroelectricity in HfO 2 based thin films and the co-integration of ferroelectric field effect transistors (FeFET) into standard high-k metal gate (HKMG) CMOS platforms, the FeFET has emerged from a theoretical dream to an applicable reality. This paper summarizes the status of GLOBALFOUNDRIES FeFET technology and some of its potential applications. We show excellent 0.12µm 2 SRAM yields of our mature 28nm CMOS platform, with co-integrated FeFETs, exhibiting a solid memory window of 1.4V. In contrast to conventional embedded memory cells, the FeFET can be integrated like a regular 26Å EOT transistor, exhibiting two reversibly programmable VT states, while offering full design flexibility. We show state of the art across wafer VT variability of the programmed and erased states of the FeFETs and discuss its layout-dependence. Embedded size-competitive FeFETs already allow solid separation of the memory states, approaching a mature 6Sigma distribution. Reasonable endurance and stable data retention are demonstrated. Moreover, an outlook of this technology beyond the von Neumann computing will be discussed, considering some of the various applications of this new, versatile device.

In this paper, recent advances on the development of Hafnium oxide (HfO2)-based ferroelectric field-effect transistors (FeFETs) are shown with respect to its memory window, trapping behavior and endurance characteristics. Although this novel ferroelectric memory cell shows superior characteristics such as device scalability, CMOS compatibility, fast access time and low power operation, the challenges for HfO2-based FeFET device lie with device variability and endurance. To investigate endurance failure in relation to charge trapping, different time delays were introduced to allow for detrapping of charges leading to improved endurance behavior. Besides the continuous improvements in process technology which minimize trap densities, we here demonstrate a mitigation of device variability, using a targeted programming scheme, with which a significantly lower device variability is achieved.

A switched-capacitor (SC) neuromorphic system for closed-loop neural coupling in 28 nm CMOS is presented, occupying 600 um by 600 um. It offers 128 input channels (i.e., presynaptic terminals), 8192 synapses and 64 output channels (i.e., neurons). Biologically realistic neuron and synapse dynamics are achieved via a faithful translation of the behavioural equations to SC circuits. As leakage currents significantly affect circuit behaviour at this technology node, dedicated compensation techniques are employed to achieve biological-realtime operation, with faithful reproduction of time constants of several 100 ms at room temperature. Power draw of the overall system is 1.9 mW.

Synaptic dynamics, such as long- and short-term plasticity, play an important role in the complexity and biological realism achievable when running neural networks on a neuromorphic IC. For example, they endow the IC with an ability to adapt and learn from its environment. In order to achieve the mil- lisecond to second time constants required for these synaptic dynamics, analog subthreshold circuits are usually employed. However, due to process variation and leakage problems, it is almost impossible to port these types of circuits to modern sub-100nm technologies. In contrast, we present a neuromor- phic system in a 28 nm CMOS process that employs switched capacitor (SC) circuits to implement 128 short term plasticity presynapses as well as 8192 stop-learning synapses. The neuromorphic system consumes an area of 0.36 mm2 and runs at a power consumption of 1.9 mW. The circuit makes use of a technique for minimizing leakage effects allowing for real-time operation with time constants up to sev- eral seconds. Since we rely on SC techniques for all calculations, the system is composed of only generic mixed-signal building blocks. These generic building blocks make the system easy to port between technologies and the large digital circuit part inherent in an SC system benefits fully from technology scaling.

Generating an exponential decay function with a time constant on the order of hundreds of milliseconds is a mainstay for neuromorphic circuits. Usually, either subthreshold circuits or RC-decays based on transconductance amplifiers are used. In the latter case, transconductances in the 10 pS range are needed. However, state-of-the-art low-transconductance amplifiers still require too much circuit area to be applicable in neuromorphic circuits where >100 of these time constant circuits may be required on a single chip. We present a silicon verified operational transconductance amplifier that achieves a gm of 5 pS in only 700 μm , a factor of 10-100 less area than current examples. This allows a high-density integration of time constant circuits in target appliations such as synaptic learning or as driving circuit for neuromorphic memristor arrays.

For neuromorphic ICs, the implemented synaptic dynamics play an important role in the complexity achievable when running networks on the overall IC. One of these ingredients for realistic dynamics are conductance-based synapses, which in contrast to current-based synapses let a neuron adapt in various ways to its input characteristics. Another ingredient is classical neuronal spike-frequency adaptation. Both are usually realized in fully-analog subthreshold circuits, making them hard to port to modern sub-100nm technologies. In contrast, we present a compact switched-capacitor (SC) model of a conductance-based synapse that can be widely configured to accurately depict e.g. NMDA, GABA or AMPA type synapses. The SC approach is inherently easy to port between technologies and its digital part benefits fully from technology scaling. We show how this synapse circuit can also be utilized to endow a neuron with spike-frequency adaptation (SFA).

Efficient Analog-Digital Converters (ADC) are one of the mainstays of mixed-signal integrated circuit design. Besides the conventional ADCs used in mainstream ICs, there have been various attempts in the past to utilize neuromorphic networks to accomplish an efficient crossing between analog and digital domains, i.e., to build neurally inspired ADCs. Generally, these have suffered from the same problems as conventional ADCs, that is they require high-precision, handcrafted analog circuits and are thus not technology portable. In this paper, we present an ADC based on the Neural Engineering Framework (NEF). It carries out a large fraction of the overall ADC process in the digital domain, i.e., it is easily portable across technologies. The analog-digital conversion takes full advantage of the high degree of parallelism inherent in neuromorphic networks, making for a very scalable ADC. In addition, it has a number of features not commonly found in conventional ADCs, such as a runtime reconfigurability of the ADC sampling rate, resolution and transfer characteristic.

Generating an exponential decay function with a time constant on the order of hundreds of milliseconds is a mainstay for neuromorphic circuits. Usually, either subthreshold circuits or RC-decays based on transconductance amplifiers are used. In the latter case, transconductances in the 10 pS range are needed. However, state-of-the-art low-transconductance amplifiers still require too much circuit area to be applicable in neuromorphic circuits where >100 of these time constant circuits may be required on a single chip. We present a silicon verified operational transconductance amplifier that achieves a gm of 5 pS in only 700 μm2, a factor of 10-100 less area than current examples. This allows a high-density integration of time constant circuits in target appliations such as synaptic learning or as driving circuit for neuromorphic memristor arrays.

I. Demo Description Traditionally, neuromorphic ICs have integrated only reduced subsets of the rich repertoire of plasticity seen in biological preparations [1], [2]. The focus with respect to long term plasticity has been mostly on Spike-Time-Dependent Plasticity (STDP) [1]. Several ICs have also implemented forms of presynaptic short term dynamics, which filter synaptic pulse input, but have no influence on other timescales of plasticity. Here, we demonstrate an IC that implements short-term-, long-term-, and metaplasticity in an integrated way following [3], where these three different timescales interact to form the overall weight at the synapse. Fig. 1 shows an example presynaptic pattern with depression and the membrane trace as input for learning [3]. The resulting analog weight state shows the influence of presynaptic depression in the step increases, comparable to [1]. Also, different settings for the learning threshold exhibit a bias towards weight increase/decrease on a metaplastic (i.e. slow) timescale similar to [2]. The overall setup features several Maple-ICs of each 16 neurons and 512 of the above synapses, interlinked via FPGA-based pulse transmission. This allows network sizes of up to 200 neurons, sufficient to demonstrate the necessity for this type of learning for a range of computational neuroscience models.

In this paper we present a novel switched-capacitor implementation of short-term synaptic dynamics with simultaneous depression and facilitation. The developed circuit model is a modified version of a model of neurotransmitter release derived from biological measurements. Despite the simplicity of the circuit the rich dynamics of the original model can be delivered. By completely relying on SC techniques for all calculations, our circuit is significantly less sensitive to process variations and easier to calibrate than commonly employed subthreshold circuits. The circuit makes use of a technique for minimizing leakage effects allowing for real-time operation with time constants up to several seconds. Functionality and robustness of the circuit are verified by simulations and comparisons to the original model.

Neuromorphic realizations of the short-term dynamics at a synapse often use simplistic circuit models. In this paper, we present a more biologically realistic VLSI implementation of these mechanisms. Our circuit approach is analytically derived from a model of neurotransmitter release, so that it can be directly related to simulation results and biological measurements. We present a reduced implementation of this approach that is highly configurable, allowing for an individual adjustment of all model parameters. Furthermore, it achieves a high robustness against process variations and successfully reproduces biological paired-pulse depression experiments.

Computational tasks such as object and pattern recognition rely on deterministic learning in the brain carried out mostly at the synapses, which link the brain’s neurons and shape the overall computational function of a group of neurons.1 Modelers build mathematical abstractions of synaptic learning by approximating the behavior of biological synapses as they try to copy relevant processing functions.2–4 Neuromorphic integrated circuits (ICs) implement transistor-based versions of these mathematical abstractions in order to realize adaptive, error-tolerant emulations of cognitive functions.5, 6 In recent years, there has been a steady increase in the size of neuromorphic systems in order to handle more advanced cognitive tasks. This calls for area-efficient circuit implementations, especially of synapses, since biology-derived topologies use far more synapses than neurons,7 which makes synapse size the determining factor in overall IC complexity.6, 8, 9 While reducing synapse size, ideally the biological accuracy of the synapses’ learning function should increase to keep pace with the biologists’ and modelers’ continuously refined understanding of cognitive functions.10 To date, these conflicting demands on the learning circuit’s implementation have not received much attention. In particular, the usual two-step approach of deriving a mathematical model and subsequently building circuits for it tends to yield very complex circuits.5, 8 However, co-developing both the mathematical model and circuit implementation could balance both objectives, resulting in a circuit-optimized mathematical model that also exhibits good biological accuracy. A synapse composes its learning function from the neurons’ local-state variables.1 But most models of synaptic learning introduce synthetic dynamical variables driven by higher order information such as spike timings.2, 3, 11 From a hardware Figure 1. Principal operation of the local-correlation plasticity (LCP) learning rule, with conductance change g(t), membrane voltage u(t), and resulting synaptic weight (w) over the progress of time (t).

The computational function of neural networks is thought to depend primarily on the learning/plasticity function carried out at the synapse. Neuromorphic circuit realizations have taken this into account by implementing a variety of synaptical processing functions, with most recent synapse circuits replicating some form of Spike Time Dependent Plasticity (STDP). However, STDP is being challenged by older rate-dependent learning rules as well as by biological experiments exhibiting more complex timing rules (e. g. spike triplets) as well as simultaneous rate-and timing dependent plasticity. In this paper, we present a circuit realization of a plasticity rule based on the postsynaptic neuron potential as well as the transmission profile of the presynaptic spike [1]. To the best of our knowledge, this is the first circuit realization of synaptical behaviour which moves significantly beyond STDP, replicating the triplet experiments of Froemke and Dan [2], the combined timing and rate experiments of Sjoestroem et al. [3], as well as conventional BCM behaviour [4].

Neuromorphic circuits try to replicate aspects of the information processing in neural tissue. Historically, this has often meant some kind of long-term learning function which slowly adjusts the weight of a synapse to achieve a certain target network function. Recently, short-term dynamics at the synapse have also gained significant attention due to their role in dynamic and temporal information processing. However, only very few neuromorphic circuits have incorporated short term dynamics, with still fewer of these implementations being biologically realistic. We derive a circuit for biologically relevant short term dynamics, showing its accuracy with respect to biological measurements. Since this circuit significantly increases the overall complexity of the synapse, a direct integration in the synapse would be prohibitive. Thus, in addition to the short term dynamics, we also present a novel configurable topology for the neurons and synapses on chip which achieves a compact and flexible overall design while still augmenting all synapses with the new short term dynamics.