Wide-bandgap nitride semiconductors are currently in development for high-power electronic applications. Compositional layered heterostructures of such nitrides result in a high polarization field at the interface, enabling a higher electron mobility, a higher power density, and a higher conversion efficiency. Further optimization of such GaN-based high-electron-mobility transistors can be achieved by evolving from a top AlxGa1−xN barrier toward AlN or even InyAl1−yN. An ongoing challenge in using such hexagonal nitride semiconductors is the formation of a low-resistive, Au-free, ohmic contact far below 1Ωmm. In this paper, we investigate the formation of ohmic contacts by Ti–Al–TiN-based metalization as a function of different annealing temperatures (up to 950°C), Ti–Al ratios (from 15 up to 35 at. %) and nitride barrier composition (AlxGa1−xN, GaN, AlN, and InyAl1−yN). Contacts processed on AlxGa1–x/GaN, and AlN/GaN heterostructures result in low contact resistance of, respectively, 0.30 and 0.55Ωmm, whereas the same contact stack on InyAl1−yN results in resistance values of 1.7Ωmm. The observed solid-phase reaction of such Ti–Al–TiN stacks were found to be identical for all investigated barrier compositions (e.g., AlxGa1−xN , GaN, AlN, and InyAl1−yN), including the preferential grain alignment to the epitaxial nitride layer. The best performing ohmic contacts are formed when the bottom Ti-layer is totally consumed and when an epitaxially-aligned metal layer is present, either epitaxial Al (for a contact which is relatively Al-rich and annealed to a temperature below 660°C) or ternary Ti2AlN (for a relatively Ti-rich contact annealed up to 850°C). The observation that the solid-phase reaction is identical on all investigated nitrides suggests that a further decrease of the contact resistance will be largely dependent on an optimization of the nitride barriers themselves.

The first section of this article focuses on the investigations of the gate leakage conduction mechanisms under forward and reverse bias conditions using temperature dependent Jg-Eg characteristics on a Silicon Nitride (SiN)/AlGaN based Metal-Insulator-Semiconductor (MIS) structure. TCAD study under forward bias conduction show majority of the voltage drop on the SiN layer only. The model fitting the electrical characteristics was observed to be Poole-Frenkel (PF) emission. Under reverse bias condition, the entire voltage drop occurs on the entire SiN/AlGaN/GaN. The conduction mechanism responsible for the leakage was found to be Fowler-Nordheim (FN) tunneling along with a thermionic emission component. Second section of this article focuses on the Time Dependent Dielectric Breakdown (TDDB) measurements and lifetime extrapolation of the SiN/AlGaN based di-electric stack. TDDB measurements were done under constant field stress for different temperatures. Normalization of the data exhibited only field accelerated degradation with no influence from the temperature.

The formation mechanism of non-recessed Au–free Ohmic contacts on the AlGaN/GaN heterostructures is investigated for various Ti/Al atomic ratios (Al–rich versus Ti–rich) and annealing temperatures ranging from 500 to 950 °C. It is shown that Ti/Al atomic ratio is the key parameter defining the optimum annealing temperature for Ohmic contact formation. Ti–rich contacts processed at high temperature result in low contact resistance ∼0.7 Ω mm, better to those obtained at low temperature or with Al–rich metal stacks. The variation of the contact resistance with Ti/Al atomic ratio and annealing temperature is correlated with the intermetallic phase changes and interfacial reaction. Depending on the Ti/Al atomic ratio, two distinct mechanisms can be distinguished. For a small quantity of Ti (e.g., Al–rich contacts), Ohmic contact formation is done through a weak interfacial reaction which is nonexistent at high temperature due to the degradation of the metal morphology. However, for a quantity of Ti higher than 25 at. % (e.g., Ti–rich contacts), the agglomeration is delayed by 200 °C as compared to Al–rich contacts, and optimal contacts are formed at high temperature through a strong interfacial reaction.

This paper extends our 650V rated GaN device technology to current ratings in excess of 100A. For the first time, devices with single digit Ron values are reported. A record low value of 6mΩ is measured at 100A. The device technology is shown to be fully current collapse free, over the complete voltage and temperature window. Intrinsic reliability test data up to Vds=900V, and T=200°C is provided. In addition, by using a thicker GaN buffer, 20A rated GaN power devices up to 1.2kV are presented, with leakage current ~100nA. This is a first step to allow AlGaN/GaN power devices to compete with Si IGBTs and SiC MOSFETs.

Although astounding performance is already proven by many research papers, the widespread adoption of GaN power devices in the market is still hampered by (1) yield and reproducibility; (2) cost; (3) reliability. All three factors are to be considered, but to convince customers to adopt GaN power devices, proven device and product reliability is a must. Cost is kept acceptably low by growing the GaN epi stack on 6 inch and 8inch Si substrates, and by processing the GaN power device technology in standard CMOS production lines.This paper will focus on the most important intrinsic reliability mechanisms for GaN power devices. It will cover gate dielectric reliability, Ohmic contact reliability, accelerated drain stress testing (high temperature reverse bias--HTRB) and high voltage device wear-out testing (high voltage off-state stress--HVOS). Acceleration models are discussedA measurement strategy to extract valuable information about the physical properties of the buffer layers (e.g. activation energies of the traps, conduction mechanisms, ...) based on simple transmission line structures, is outlined.

This paper reports on the technology and design aspects of an industrial DHEMT process for 650V rated GaN-on-Si power devices, using an in-situ MOCVD grown SiN as surface passivation and gate dielectric, with low interface state density and excellent TDDB. Optimization of the GaN epi stack results in very low off-state leakage (<10nA/mm). Due to the reduction of buffer trapping, low dynamic Ron (<10%) is obtained, both at room temperature and at high temperature.

A strong positive correlation between dynamic Ron and the ionization of buffer traps by injection of electrons from the Si substrate is presented. By exploring different Carbon doping profiles in the epi layers, the substrate buffer leakage is substantially reduced, which in turns results in lower dynamic Ron. The traps in the epi structure are characterized by different electrical techniques such as drain current transient, on-the-fly trapping and ramped back-gating experiments.

This paper reports on an industrial DHEMT process for 650V rated GaN-on-Si power devices. The MISHEMT transistors use an in-situ MOCVD grown SiN as surface passivation and gate dielectric. Excellent off-state leakage, on-state conduction and low device capacitance and dynamic Ron is obtained. Initial assessment of the intrinsic reliability data on the in-situ SiN is provided.

A novel silicon device architecture for DC-DC power conversion is reported. Efficient switching at high frequencies (1-5 MHz) is achieved by simultaneously reducing gate charge, reverse capacitance, and gate resistance while still maintaining good on-state resistance and off-state breakdown voltage. Power efficiencies in excess of 88% were realized in a synchronous buck converter running at 1.3 MHz.

During deep reactive ion etching of silicon used for through silicon via or deep trench isolation processing, the bevel of the wafer is also etched away. The etching of the bevel results in a deep step at the litho edge bead removal or in a degraded bevel shape, source of yield loss or processing issues. Two methods are proposed here to prevent the bevel degradation during deep reactive ion etching using an oxide hard mask. In one case this oxide mask is deposited in the second case the oxide hard mask is grown.

The maximum transient voltage of a MOSFET device is one of the key parameters for power applications. Therefore, transmission line pulse (TLP) characterization is used to assess this. TLP measurements on large gate width devices are difficult to perform due to gate oscillations.In this paper, a method to avoid oscillation when measuring large gate width devices is presented. Device simulations are presented showing gate side oscillation triggered by the rising edge of the 100 ns TLP pulse. Adding a resistor in series with the gate largely damps the oscillation. Comparison between system level simulation and captured TLP waveforms is done and the correlation is discussed. (C) 2007 Elsevier Ltd. All rights reserved.

An extensive investigation of the reliability of deep trench isolation structures upon reverse bias stress is performed. By using the variable base level charge pumping technique, it is shown that the degradation of the trench primarily originates from N/sub it/ formation at the inner trench corners. The reliability is improved by introducing cut corners.

In this paper, we propose intensive investigations of the electrical characteristics of a deep trench isolation structure for a new 0.35μm CMOS based smart power technology. In particular, it is demonstrated, both experimentally and theoretically, that its blocking voltage can be strongly affected by the presence of charges in the floating polysilicon filling the trench. These charges are shown to appear as a consequence of hot carrier injection through the liner oxide during avalanche operation. The measured breakdown voltage instabilities are explained by TCAD simulation tools as well as by a simple theoretical model based on the capacitive coupling approach.

In this paper, the mechanism of plasma-charging damage (PCD) of metal-insulator-metal (MIM) capacitors as well as possible protection schemes are discussed.A range of test structures with different antennas simulating interconnect layout variations have been used to investigate the mechanism of PCD of MIM capacitors.Based on the experimental results, two models are presented, describing the relation between the damage and the ratio of the area of the exposed antennas connected to the MIM capacitors plates.New design rules are proposed in order to predict and automatically flag possible PCD sites.Furthermore, layout solutions to reduce PCD are suggested.

This paper describes the threshold voltage shift observed on a floating PDMOS transistor, made in a 0.7 /spl mu/m compatible CMOS process. It is shown that this shift was caused by plasma induced damage. Positive charges introduced during the via etching are trapped in the gate of the PDMOS device. An explanation is also provided why the threshold voltage shift was mainly observed on this particular device. The plasma damage can be avoided by improving the via etch uniformity. It has also been proven that by extending the sinter time we were able to anneal out oxide trapped charges, hence making the process more immune to this type of damage.

This paper describes the development of a deep trench isolation module for a new 0.35 /spl mu/m CMOS based smart power technology as well-as some major devices taking advantage of the features offered. by this deep trench isolation. The so-called I3T50 technology belongs to the third generation of intelligent interface technologies developed within AMI Semiconductor over the past years. This newest technology is suitable for applications up to 50 V, such as automotive, peripheral, industrial and consumer applications. Trench isolation is used to isolate the devices, hereby substantially reducing the isolation area. A full device library has been released within this technology (n-type and p-type CMOS and DMOS devices, bipolar transistors, high voltage floating diodes, passive components, OTP memory and a set of ESD protection structures).

This paper describes a new 0.35 mum CMOS based smart power technology. The so-called 13T50 technology belongs to a series of intelligent interface technologies developed within AMI Semiconductor over the past years. This technology is suitable for applications up to 50 V, such as automotive, peripheral and consumer applications. Trench isolation is used to isolate the devices, substantially reducing the isolation area. The set of devices available within this technology consists of n-type and p-type CMOS and DMOS devices, bipolar transistors, a high voltage floating diode, passive components, OTP memory and a set of ESD protection structures. In the future, the technology will be extended also with a modular embedded flash memory.

In this paper, the breakdown of a deep trench isolation structure has been analysed and modeled. In particular, it is shown that the breakdown voltage of the p-n junction in the silicon can be strongly affected by the presence of charges on the floating polysilicon within the trench. These charges might appear not only as process induced charges but also as a consequence of hot carrier injection during avalanche operation. The measured breakdown instabilities can be reproduced by TCAD simulations as well as by a simple theoretical model within which these results can be understood and predictions can be made.

This paper describes how the use of a short soft Ar sputter etch done on the top of the dielectric film of a metal-insulator-metal (MIM) capacitor improves the quality of this film. It was observed that the insulator film as deposited has higher leakage currents and shows early failures during breakdown measurements, while significant lower leakage and tighter breakdown distributions are obtained when a sputter etch is included. However TXRF and SIMS analysis did not reveal any contamination, it is believed that the top few nanometers of the film are of poor quality, and in this way degrade the performance of the capacitor. RF circuits designed in bipolar or BiCMOS technologies require integrated capacitors with high quality factor. This implies that these capacitors should exhibit extremely low dielectric loss combined with minimal series resistance and parasitic capacitance, excellent capacitor matching and linearity. Moreover they should meet the necessary reliability requirements and be processed with low defectivity. Metal-insulator- metal (MIM) capacitors have proven to be the optimal solution. They demonstrate low parasitic capacitance, especially when fabricated at a higher metal level, low series resistance and the required matching and linearity performance, thanks to the absence of v oltage induced depletion, as observed in poly-insulator-poly capacitors. The data reported here is based on MIM capacitors that have been integrated in a 0.35 µm-BiCMOS technology (1). They aim at a capacitance per unit area of 1.0 or 1.5 fF/µm², an increase that can be achieved by reducing the dielectric thickness. The bottom plate of the capacitor is making use of a regular metal layer, which also serves as metal interconnect layer. A PECVD nitride with a thickness of about 60 (1.0 fF/µm²) or 40 nm (1. 5 fF/µm²) has been chosen as dielectric, because of its higher dielectric constant, which allows to scale down the capacitors (2),(3),(4). A thin TiN/AlCu/TiN stack acts as top plate, which is patterned first with a selective etch chemistry that stops in the dielectric. After etching the top plate and stripping the remaining photoresist, the bottom plate is patterned, together with the interconnect at this level. Once the complete capacitor is formed an intermetal dielectric is deposited and planarized. The top plate of the capacitor is connected through the subsequent via to the next metal (See figure 1). In this way the MIM capacitor module can be integrated at each metal level, except the top metal level.