The occurence of periodic Coulomb blockade in transistors at low temperature allows to extract the capacitances between the channel and the gate, source, and drain. This extremely sensitive method is well adapted to nanoscale devices, where these capacitances are well below the fF range and in parallel with low resistances. We applied this method to 3-D stacked MOSFETs featuring a double-gate top channel and a single-gate bottom channel. The measured gate capacitances are in excellent agreement with estimations based on the geometry, and are independent on the gate voltage. The source and drain capacitances can also be measured separately for each parallel conduction channel, even when their values are markedly different. We illustrate this case with a device with one dominating double-gate channel and a buried, single-gate channel which is not detectable at 300 K and contributes for less than 5% to the total conductance at 4.2 K.

A compact model for the drain current and node charges in symmetrical Double-Gate (DG) MOSFET, including-short-channel and carrier confinement effects is developed. The model is particularly well adapted to ultra-scaled devices, with short-channel lengths and ultra-thin silicon films. An extensive comparison step with 2D quantum numerical simulation fully validates the model. The model is also shown to reproduce with an excellent accuracy experimental drain current measured in DG devices fabricated with Silicon-on-Nothing ( SON) process. Finally, the DG model has been successfully implemented in Eldo IC analog simulator, demonstrating the application of the model to circuit simulation.

A new mobility degradation specific to short channel MOSFETs is studied and elucidated. Pocket implants/dopants pile-up, interface states/oxide charges, remote Coulomb scattering or ballisticity are insufficient to explain this degradation. The role of non-Coulombian (neutral) defects, which can be healed by increasing the annealing temperature, is evidenced

A continuous compact model for the drain current, including short-channel effects and carrier quantization in Double-Gate MOSFET is developed. The model is particularly well-adapted to ultra-scaled devices, with short channel lengths and ultra-thin silicon films. An extensive comparison step with 2D quantum numerical results fully validates the model. Finally, the model is shown to reproduce with an excellent accuracy experimental drain current in Double-Gate devices.

Conventional bulk CMOS scaling starts to fail. In order to prolong the life of Moore's laws, at least one technological booster (innovation) per node has to be introduced starting from the node 32nm on. This presents a big technological challenge for the semiconductor industry. On the other hand, accumulation of the boosters permits to retrieve healthy scaling down to sub-10nm gate lengths. This strategy even if technologically very challenging, is prospected to prolong the CMOS competitiveness till at least 2020.

In this paper, the authors presented an integration strategy for metal gate GAA transistors made by SON process using poly-gate replacement through contact hole (PRETCH). Double gate (DG) type MOSFETs, including planar DG gate-all-around and fin-FETs are today known as the best candidates for the ultimate sealing of the logic CMOS technologies on silicon. One of the main difficulties in optimizing DG devices is the control of the threshold voltage (Vth) from high performances to low power devices. With polysilicon gates, a higher channel doping has to be used when lowering the silicon thickness (TSi). This adjustment strategy has its limits and thus, gate workfunction engineering seems necessary for thin DG transistors.

Double gate type transistors are needed for the ultimate integration on silicon, and thus extraction techniques have to be adapted. In this paper, the influence of the series resistance on the extrinsic mobility reduction parameters is analysed, in the case of a resistance varying with the gate bias. It is evidenced that both the low field and high field parameters are impacted. Then, a new approach is proposed for the extraction of the series resistance variation with the gate voltage, and applied to the analysis of gate-all-around transistors series resistance, with doped and undoped body.