This paper proposes a new expression unifying all transport mechanisms (drift-diffusion, velocity-saturation and quasi-ballistic). This enables an experimental extraction of the limiting velocity and also, for the first time, a determination of its nature (thermal injection or velocity saturation). We show that the observed increase in the limiting velocity in short and strained devices was confusingly interpreted as an evidence of increasing ballisticity. At least down to 20nm channel length, the transport remains velocity-saturation limited. However, the good news we confirm experimentally is that V sat increases itself in short and strained devices. This promises an increase in I on , even if the nature of the transport is velocity-saturated. This new findings open doors for the study and optimization of transport in advanced CMOS technologies.

En depit des defis technologiques a surmonter lors de la reduction d'echelle, la technologie sur silicium assif (bulk) reste attractive grâce son cout modere. L'augmentation du dopage est un des leviers utilises pour ontrecarrer les effets de canaux courts. Si cette solution reste contraignante en termes de performances (car elle entraine une diminution de la mobilite et une augmentation de la variabilite), l'augmentation du taux de balisticite sur les petites longueurs de grille laisse entrevoir la perspective d'un fort courant Ion, peu dependant de la mobilite. Cette vision semble attractive, mais la litterature porte peu d'attention a discriminer le phenomene de vitesse de saturation (vsat) du phenomene d'injection a la source (vinj). Pourtant, chacun d'eux peut etre LE mecanisme limitant Ion selon le flux de porteurs est limite par la capacite d'injection ou bien par les proprietes de transport du canal. Ce papier ce focalise sur la determination de la vitesse limitant le transport en considerant les deux approches comme probables.

For the first time we demonstrate the CMOS integration of undoped fully-depleted Ultra Thin Body and BOX devices (UTB2) with (110)/(100) substrate crystal orientation for pFET and nFET respectively. For this, we used an original 3D-folded Bulk+/Silicon-On-Nothing (SON) process on DSB substrate. Resulting multi-surface orientations devices are studied.

This work presents an experimental study in order to evaluate the quality of transport in state-of-the-art gate-all-around devices. 25 nm times 20 nm times 10 nm (LxWxT Si ) silicon channel devices with metal/high-k gate all-round stack were characterized electrically in terms of mobility and limiting velocity in order to evaluate the possible occurrence of ballisticity. Conclusions are finally presented in the scope of elementary circuit perspectives.

This work proposes a planar fully depleted “folded” technology integrated on bulk substrate as an innovative solution for upcoming low power nodes to enhance drive current on narrow devices. We report a detailed fabrication method, combining advanced selective epitaxy faceting and SON (Silicon-On-Nothing) process, to provide ultra thin body and buried oxide (UTB2) devices with improved drive current Ion for a given designed footprint Wdesign when scaling the device width. We compare the fabrication and electrical behavior between 〈110〉 channel, i.e. 0°-rotated wafer, and 〈100〉 channel, i.e. 45°-rotated wafer, for the same (100) surface orientation.

For the first time 3D sequential CMOS integration turns up to be an actual competitor for sub 22nm technology nodes. Thanks to the original use of molecular bonding, high quality top Si active layers are obtained. Thermally robust bottom salicide goes through the whole top FET processing without any significant sheet resistance degradation. The low temperature integration of raised source and drain for top layers is demonstrated. A decrease by 44 of the Equivalent Oxide Thickness is measured when a low thermal budget process is implemented. The electrostatic coupling between stacked FETs is demonstrated thanks to an ultra thin inter layer dielectric thickness of 60nm. It leads to a threshold voltage dynamic shift of 130mV enabling SRAM stabilization.

We report a new nanodot MOSFET, based on the use of Bulk wafer and Silicon-On -Nothing technology, requiring neither CMP nor extra photo-lithographic step. SRAM-application oriented nanodot devices were fabricated using this new process. Record performance among the nanometric gate-all-around MOSFET state-of-the-art is obtained thanks to a high quality transport.

This work highlights the new bulk+ technology using high-K dielectric, single metal gate and fully depleted SON (silicon on nothing) channel for sub-45 nm low cost applications. Thin silicon channel (down to Tsi= 8 nm) and thin BOX (Tbox = 15 to 25 nm) are obtained using the SON process (Jurczak, 1999). Transistor performance (Wdesign/Lgate= 90 nm/40 nm) at Vdd = 1.1 V and Ioff < 2 nA/ mum is as high as 1298 muA/ mum for nMOS and 663 muA/ mum for pMOS. In addition, reliability, noise and 6T-SRAM bit cells down to 0.249 mum2 are characterized. Significant improvements with respect to conventional bulk technology are demonstrated.

This work proposes a Bulk+ planar fully depleted ldquofoldedrdquo technology as an innovative cost worthy solution for upcoming low power nodes. We report a detailed fabrication method, combining advanced selective epitaxy faceting and SON (Silicon-On-Nothing) process, to provide thin film/thin BOX devices with improved transistor gain beta for a given designed footprint W design . We compare the fabrication between <110> channel, i.e. non-rotated wafer, and <100> channel, i.e. 45deg-rotated wafer, for the same (100) surface orientation.

This paper describes the fabrication and electrical behavior of a fully-depleted SOI technology using a direct metal gate and high-k dielectric integrated on 300mm SOI wafers for low power applications. We report ultra-thin FDSOI MOS transistors with WN metal gate (capped with TiN) on HfSiON gate dielectric. Performance at both device and circuit level are demonstrated and compared with TiN midgap metal gate.

2007 International Conference on Solid State Devices and Materials,Highly Manufacturable and Cost-effective Single TaxC / HfxZr(1-x)O2 Gate CMOS Bulk Platform for LP Applications at the 45nm Node and Beyond

A new mobility degradation specific to short channel MOSFETs is studied and elucidated. Pocket implants/dopants pile-up, interface states/oxide charges, remote Coulomb scattering or ballisticity are insufficient to explain this degradation. The role of non-Coulombian (neutral) defects, which can be healed by increasing the annealing temperature, is evidenced

In buffered water:methanol media, the pKa values of acid-base equilibria involved in the protonation of substituted quinolines are determined by UV-visible absorption spectrometry. The observed behavior depends on the nature of R2: the N—CH3 derivatives exist as quinoline, the N—H derivatives as 4-iminoquinoline tautomers. The iminoquinoline zwitterionic species present at physiological pH may have high receptor affinity. A linear relationship between pKa of the endocyclic nitrogen and log IC50 is discussed.

Platelet 3H-imipramine binding was investigated in 15 normal subjects, 17 patients with major depressive disorder and 43 patients with panic disorder, to further study the relationship between depressive and anxiety disorders. Whereas patients with major depression had a significantly lower mean Bmax value than healthy volunteers, mean Bmax values in patients with panic disorder did not differ significantly from normal controls. Furthermore, apparently normal Bmax values were observed even in those panic disorder patients who had concurrent major depression or a past history of depression. Thus, despite previous findings of an overlap between panic and depressive disorders, the present results suggest that the two syndromes may have distinct neurochemical substrates.