Analog memory presents a promising solution in the face of the growing demand for energy-efficient artificial intelligence (AI) at the edge. In this study, we demonstrate efficient deep neural network transfer learning utilizing hardware and algorithm co-optimization in an analog resistive random-access memory (ReRAM) array. For the first time, we illustrate that in open-loop deep neural network (DNN) transfer learning for image classification tasks, convergence rates can be accelerated by approximately 3.5 times through the utilization of co-optimized analog ReRAM hardware and the hardware-aware Tiki-Taka v2 (TTv2) algorithm. A simulation based on statistical 14 nm CMOS ReRAM array data provides insights into the performance of transfer learning on larger network workloads, exhibiting notable improvement over conventional training with random initialization. This study shows that analog DNN transfer learning using an optimized ReRAM array can achieve faster convergence with a smaller dataset compared to training from scratch, thus augmenting AI capability at the edge.

This paper addresses the key challenges of copper (Cu) undercut control using the end point detection (EPD) system based on the Applied Materials Raider tool. The Cu etch rate was measured with the timed etch to validate the end point detection on blanket wafers. The end point traces were then collected on C4 pillars under 0, 25, 50, and 100% over etch conditions. C4 pillars undercut amounts were measured using Focused Ion Beam Scanning Electron Microscopy (FIB-SEM). The ability to detect the endpoint (EP) and stop at a defined over etch (OE) from the end point was demonstrated. Based on FIB-SEM and Energy dispersive X-ray (EDX), we have developed an endpoint recipe with minimal undercut.

We show for the first time in hardware that in contrast to conventional stochastic gradient descent (SGD), our modified SGD algorithm (TTv2) together with a co-optimized ReRAM material achieves respectable accuracy (98%) on reduced MNIST classification ( 0 & 1), approaching a floating point ( FP) baseline. To extrapolate these insights towards larger DNN training workloads in simulations, we establish an analog switching test sequence and extract key device statistics from 6T1R ReRAM arrays (up to 2k devices) built on a 14nm CMOS baseline. With this, we find that for larger DNN workloads, device and algorithm co-optimization shows dramatic improvements in comparison to standard SGD and baseline ReRAM. The gap to the reference floating-point accuracy across various tested DNNs indicates that further material and algorithmic optimizations are still needed. This work shows a pathway for scalable in-memory deep learning training using ReRAM crossbar arrays.

We demonstrate a novel process for building a Resistive RAM (ReRAM) stack which reduces the forming voltage (V-form) and increases the switching resistance, both characteristics that are important ingredients for the use of ReRAM in scalable analog compute for AI. Utilizing this process, we explore analog switching characteristics above 100k and demonstrate 4-bit programming at Rmax = 1M. Utilizing the same writing characteristics, CIFAR-10 inference simulation shows 90% accuracy, comparable to the full precision model accuracy.

We optimize the hardware process for building a resistive RAM (RRAM) stack to increase the switching resistance while reducing the forming voltage (Vform), which are important ingredients for scalable analog computing. With increased resistance, we identified few immediate challenges. We demonstrate that one of those challenges, non-idealities in switching character, can be addressed by algorithm optimization.

In this paper we demonstrate a novel methodology to electrically test and characterize resistive random-access memory (RRAM) single bit devices for deep learning application. We extract critical device performance metrics for validating and optimizing fabrication processes which feed into yield learning. We adopt the algorithm-based bias condition search methodology and extract forming and switching voltage parameters without overdriving the devices. This test methodology can be used for Technology Development Learning Cycle in a research and development environment.

Neuromorphic computing represents a potential paradigm shift from conventional von Neumann computing architecture and shows promise for achieving massive parallelism and power efficiency for such data-centric tasks as image recognition and language processing. Based on the concept of synaptic plasticity, human-like machine learning can be potentially realized by use of arrays of electronic synapses that function in an analogous manner to biological neurons. One of the key features of this type of computing is the ability to control synaptic weights in an analog-like fashion for use in both inference and training applications. A number of existing device technologies in non-volatile memory systems exhibit attractive characteristics for such synaptic devices.[1,2] In particular, resistive switching devices (resistive random-access memory or ReRAM) can change and store their conductance value (G) in response to electrical stimuli making them potentially enabling for deep learning applications involving synaptic weights. For ReRAM devices, HfO2-based thin films can be utilized for filamentary oxide ReRAM and are an attractive option due to their fab-friendly processing and current implementation in high-volume manufacturing. In this study, we evaluated atomic layer deposition (ALD) for the growth of HfO2 for integration in both front-end-of-line (FEOL) and back-end-of-line (BEOL) compatible test structures on 300 mm wafers in order to optimize electrical performance for use as synaptic device elements in neuromorphic architectures. The effect of oxidant in the ALD process was evaluated and it was shown that H2O outperformed O3 in terms of better uniformity and lower forming voltage. By utilizing a hydrogen-based plasma either after the deposition or inserted as an intermediate step during deposition we were able to further decrease forming voltage for a fixed dielectric thickness. Reducing deposition temperature to 200°C in conjunction with the hydrogen-based plasma treatment offered an additional tuning knob to further reduce forming voltage. Stable high-resistance switching (> 100 kΩ) with analog behavior in scaled BEOL devices was also obtained using this optimized HfO2-based ReRAM. Additionally, a tight distribution of forming voltage was obtained ensuring that 99.9999% devices in a 14 nm ReRAM module can be formed below the targeted voltage. References Kuzum et al., Nanotechnology, 24, 382001 (2013) W. Burr et al., Advanced in Physics:X, 2, 89 (2016)

Emerging memory technologies such as Resistive Memory (RRAM) have gained a lot of attention to meet the requirements of a potential analog computing element, due to its non-volatile characteristics, scalability and energy efficiency. An RRAM device typically consists of a resistive switching layer (e.g. HfO2) sandwiched between two metal electrodes. Since oxygen vacancies are critical to the functioning of the device, it is desirable to achieve residue free etching using oxygen-less plasmas, and preferably minimize exposure to ambient environment. In this work, we discuss the RRAM patterning challenges and their impact on the device characteristics including the switching/forming voltage.

The continuously growing demands in high-density memories drive the rapid development of advanced memory technologies. In this work, we investigate the HfOx-based resistive switching memory (ReRAM) stack structure at nanoscale by high resolution TEM (HRTEM) and energy dispersive X-ray spectroscopy (EDX) before and after the forming process. Two identical ReRAM devices under different electrical test conditions are investigated. For the ReRAM device tested under a regular voltage bias, material redistribution and better bottom electrode contact are observed. In contrast, for the ReRAM device tested under an opposite voltage bias, different microstructure change occurs. Finite element simulations are performed to study the temperature distributions of the ReRAM cell with filaments formed at various locations relative to the bottom electrode. The applied electric field as well as the thermal heat are the driving forces for the microstructure and chemical modifications of the bottom electrode in ReRAM deceives.

As device scaling continues, controlling defect densities on the wafer becomes essential for high volume manufacturing (HVM). One type of defect, the non-selective SiGe nodule, becomes more difficult to control during SiGe epitaxy (EPI) growth for p-type field effect transistor (pFET) source and drain. The process window for SiGe EPI growth with low nodule density becomes extremely tight due to the shrinking of contact poly pitch (CPP). Any tiny process shift or incoming structure shift could introduce a high density of nodules, which could affect device performance and yield. The current defect inspection method has a low throughput, so a fast and quantitative characterization technique is preferred for measuring and monitoring this type of defect. Scatterometry is a fast and non-destructive in-line metrology technique. In this work, novel methods were developed to accurately and comprehensively measure the SiGe nodules with scatterometry information. Top-down critical dimension scanning electron microscopy (CD-SEM) images were collected and analyzed on the same location as scatterometry measurement for calibration. Machine learning (ML) algorithms are used to analyze the correlation between the raw spectra and defect density and area fraction. The analysis showed that the defect density and area fractions can be measured separately by correlating intensity variations. In addition to the defect density and area fraction, we also investigate a novel method – model-based scatterometry hybridized with machine learning capabilities – to quantify the average height of the defects along the sidewall of the gate. Hybridizing the machine learning method with the model-based one could also eliminate the possibility of misinterpreting the defect as some structural parameters. Furthermore, cross-sectional TEM and SEM measurement are used to calibrate the model-based scatterometry results. In this work, the correlation between the SiGe nodule defects and the structural parameters of the device is also studied. The preliminary result shows that there is strong correlation between the defect density and spacer thickness. Correlations between the defect density and the structural parameters provides useful information for process engineers to optimize the EPI growth process. With the advances in the scatterometry-based defect measurement metrology, we demonstrate such fast, quantitative, and comprehensive measurement of SiGe nodule defects can be used to improve the throughput and yield.

In this paper, for the first time we demonstrate that horizontally stacked gate-all-around (GAA) Nanosheet structure is a good candidate for the replacement of FinFET at the 5nm technology node and beyond. It offers increased W eff per active footprint and better performance compared to FinFET, and with a less complex patterning strategy, leveraging EUV lithography. Good electrostatics are reported at L g =12nm and aggressive 44/48nm CPP (Contacted Poly Pitch) ground rules. We demonstrate work function metal (WFM) replacement and multiple threshold voltages, compatible with aggressive sheet to sheet spacing for wide stacked sheets. Stiction of sheets in long-channel devices is eliminated. Dielectric isolation is shown on standard bulk substrate for sub-sheet leakage control. Wrap-around contact (WAC) is evaluated for extrinsic resistance reduction.

In this study, a manufacturable CMOS dual solid phase epitaxy (SPE) process with pc < 2.2×10 −9 Q-cm 2 on both NFET and PFET is demonstrated on the hardware with 7nm ground rule. Contact resistivity reduction strategies of both the conventional approach of high in-situ doped epi and the novel SPE processes are systematically studied on device and ring oscillator (RO) level. Clear improvement in the RO delay is accomplished by the novel dual SPE process on the CMOS flow. Stronger performance benefit is demonstrated with smaller contact sizes towards future CMOS technology nodes.

We present a 7nm technology with the tightest contacted poly pitch (CPP) of 44/48nm and metallization pitch of 36nm ever reported in FinFET technology. To overcome optical lithography limits, Extreme Ultraviolet Lithography (EUV) has been introduced for multiple critical levels for the first time. Dual strained channels have been also implemented to enhance mobility for high performance applications.

A 10nm logic platform technology is presented for low power and high performance application with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm ever reported in the FinFET technology on both bulk and SOI substrate. A 0.053um2 SRAM bit-cell is reported with a corresponding Static Noise Margin (SNM) of 140mV at 0.75V. Intensive multi-patterning technology and various self-aligned processes have been developed with 193i lithography to overcome optical patterning limit. Multi-workfunction (WF) gate stack has been enabled to provide Vt tunability without the variability degradation induced by channel dopants.

In this paper, we present a 10nm CMOS platform technology for low power and high performance applications with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm ever reported in the FinFET technology on both bulk and SOI substrates. A 0.053um2 SRAM bit-cell is reported with a corresponding Static Noise Margin (SNM) of 140mV at 0.75V. Intensive multi-patterning technology and various self-aligned processes have been developed with 193i lithography to overcome optical patterning limits. Multi-workfunction (MWF) gate stack has been enabled to provide Vt tunability without the variability degradation induced by Random Dopant Fluctuation (RDF) from channel dopants.