We investigate intermediate states of Ge-rich GeSbTe phase-change memory (PCM) cells by electrical impedance spectroscopy (EIS) after partial SET and RESET programming. The electrical impedance response is well described by a series resistor and a parallel RC circuit, allowing extraction of state-dependent resistance and capacitance values. A resistance ratio of similar to 250 and a capacitance reduction of similar to 85% are observed between RESET and SET states. While resistance can be continuously tuned, capacitance major variation remains confined near the SET state, with crystalline-dominated cells exhibiting the highest values. Technology computer-aided design simulations confirm the equivalent circuit and reveal that conduction mainly occurs along the amorphous-crystalline interface. Cells with embedded Ge or Sb grains display the largest capacitances, as these inclusions provide extra conduction pathways and localized charge storage sites that jointly influence the device's resistance and capacitance. Overall, this work demonstrates that the electrical properties of inhomogeneous multiphase PCMs are governed by the complex network of nanoscale heterostructures present in their active regions. It also demonstrates that EIS is a suitable, nondestructive technique for characterizing PCM devices.

The crystallization of initially amorphous Ge-rich Ge-Sb-Te nanostructures is investigated using fast thermal pulse heating, coupled with in situ scanning transmission electron microscope-energy dispersive spectroscopy (STEM-EDX) and high resolution (HR)-Transmission electron microscopy (TEM) analyses. Chemical analysis reveals a Te-Ge interdiffusion mechanism occurring at the bottom interface between the Ge-rich GST (GGST) layer and the underlayer (UL). The initially Ge-rich cell shows increasing Te-enrichment as the temperature increases. The onset of crystallization was found to start at 350 degrees C with pure cubic Ge grains appearing first, followed by cubic GST at 390 degrees C. Initially localized at the interfaces, the crystallization of both phases spreads heterogeneously throughout the cell. The spatial distribution of grains is compared with the variations in chemical composition at the nanometric scale.

The Computing-In-Memory (CIM) paradigm offers a promising solution to the memory-wall bottleneck that limits conventional Von Neumann architectures. By performing data processing at the same physical location where the data are stored, CIM-based architectures minimize costly data movement and drastically improve energy efficiency. When implemented with Ferroelectric Field Effect Transistors (FeFETs), additional advantages from the non-volatility, fast switching, and low operating voltage of FeFETs are added. However, the widespread adoption of FeFETs is limited by their poor endurance, which is overcome by a Back End of the Line (BEoL) integration of FeFET-2, where a ferroelectric capacitor (FeCAP) is wired to the gate of a CMOS transistor providing high endurance compatible with low-power edge applications. These properties enable dense, low-power, and high-speed matrix operations essential for AI workloads. As a result, FeFET-2-based CIM accelerators offer a promising solution for energy-efficient, high-performance AI at the edge. The Ferro4EdgeAI project aims to develop an ultra low-power, scalable edge accelerator for AI, targeting a significant gain in energy efficiency with respect to state-of-the-art AI hardware accelerators. To attain this, our project focuses on innovation all along the value chain from materials, physic concepts, device architecture, integration technologies, and accelerators in a holistic design space exploration approach.

Phase-change memory (PCM) based on Ge-rich GeSbTe (GGST) alloys have been demonstrated to be a reliable nonvolatile memory technology that meets the stringent specifications of automotive applications. Further material engineering of the GGST alloy through innovative doping could pave the way for future sub-18 nm technology nodes and device ultimate scaling. This study investigates the impact of progressive Ge substitution by a dopant element (D) in standard GGST alloys featuring an Sb-over-Te ratio lower than one and addresses both amorphous phase properties and crystallization behavior. Electrical, structural, and vibrational analyses show that D incorporation increases resistivity and improves thermal stability of the amorphous phase despite a reduced Ge content. D incorporation also modifies the stoichiometry of the segregated GeSbTe (GST) phase during crystallization. Indeed, a higher D content promotes the formation of an Sb-rich phase (i.e., featuring a high Sb-over-Te ratio) and alters the crystallization kinetics. This evolution suppresses the metastable cubic phase and favors a direct transition from the amorphous phase towards the stable hexagonal phase. These findings highlight that Ge-substitution-based doping provides an effective route to tune amorphous stability and phase evolution, offering a robust strategy for optimizing GGST materials for advanced PCM applications.

This study investigates the behavior of a Threshold-Changeable Memory (TCM) device based on an amorphous GeSbSeN (GSSN) alloy. A dedicated programming protocol is optimized to induce polarity-dependent threshold voltage modulation. Building on this programming protocol, the influence of elemental composition, particularly variations in Sb and N content, is examined to determine its effect on the achievable MW and the efficiency of the programming process. In addition, a systematic time-dependent drift analysis is performed as a function of Sb content to investigate the impact of Sb incorporation on threshold voltage stability. Activation energy extraction and temperature-dependent measurements are performed to provide further insight into the mechanisms responsible for polarity-induced threshold voltage modulation. These results offer key insights about the origin of the TCM mechanism in GSSN alloys and establish a solid foundation for the future development of this emerging memory technology.

This study explores laser‐induced crystallization and amorphization processes in thin films of Ge‐rich GST (GGST), a tailored phase change material (PCM), monitored in situ using synchrotron X‐ray diffraction. GGST's high crystallization temperature makes it a promising material for embedded memory applications. Experiments employed an 800 nm femtosecond laser source, varying fluence and pulse parameters to induce phase transitions. Key findings include fluence‐dependent thresholds for crystallizing Ge and GST, along with precise control over reversible amorphization. Crystallization maps highlight the differences in fluence and pulse requirements for the transformations. Repeated cycling between amorphous and crystalline states, mimicking PCM operations, confirms the feasibility of controlled phase transitions. Surface imaging using scanning electron microscopy revealed fluence‐induced changes, including ripple formation and ablation at higher intensities. The potential of ultrafast laser irradiation to precisely manipulate GGST phase changes is demonstrated, establishing a foundation for future research on time‐resolved experiments on this and other PCMs.

Ge-rich Ge–Sb–Te alloys exhibit a high (>350 °C) crystallization temperature, which is compatible with applications requiring a high thermal stability such as the use of non-volatile memories in cars. As the composition of these alloys does not correspond to any stable crystalline phase, crystallization from the amorphous phase is accompanied by phase separation (Ge2Sb2Te5 + Ge). The complexity of the elemental processes associated with this multiphase amorphous-to-crystal transition calls for in-depth materials studies. In this work, we focus on the influence of a thin (5 nm) underlayer (Ge2Sb2Te5 or Sb2Te3) on the crystallization of a Ge-rich Ge–Sb–Te alloy. Using in situ synchrotron x-ray diffraction, we demonstrate that the underlayers facilitate crystallization by decreasing crystallization temperature and suppressing incubation time. These results are interpreted in the framework of classical nucleation theory and are supported by crystallographic texture measurements, which evidence ⟨111⟩ fiber texture in the crystallized cubic Ge2Sb2Te5, particularly marked in the case of an Sb2Te3 underlayer. These results bear important consequences for the cycling of memory cells based on these materials.

Among the phase change materials, Ge 2 Sb 2 Te 5 is considered the reference material for phase change memories [1]. However, it has a low crystallization temperature close to 150°C, which makes it unsuitable for applications where high thermal stability is required. To meet more stringent requirements of dedicated applications such as automotive, solutions to increase the crystallization temperature have been explored, such as Ge enrichment [2], light element doping or exploration of new compounds. In this work, we demonstrate the possibility of controlling the stoichiometry of the segregated GeSbTe (GST) phase in the Ge-rich GeSbTe system by doping. The investigation was carried out by combining the results of different characterization techniques such as Resistivity vs. Temperature (RvsT), Raman spectroscopy and X-ray diffraction (XRD) analyses. We analyzed samples with different dopant contents (from D1 i.e. the lowest content to D3 i.e. the highest content) and compared them with the reference sample (i.e. without dopant). We investigated the amorphous to crystalline transition by ex situ measurements, performed on samples heated up at different annealing temperatures up to 500°C, which provided insight into the structural evolution before, during and after crystallization. Phase identification was achieved from XRD patterns and vibrational mode assignment from Raman spectra. The RvsT curves show the increase in amorphous resistivity as well as the increase in crystallization temperature of the layers with increasing dopant content ( Figure 1 ). In addition, the crystallization kinetics change as the dopant content increases. XRD patterns ( Figure 2 ) combined with Raman spectra confirm the segregation of a cubic Ge phase and of a “Ge-poor” cubic GeSbTe (GST) phase at the annealing temperature of 375°C. The shift of the Bragg peak at about 29.5° toward lower angles (with respect to the known cubic Ge 2 Sb 2 Te 5 phase), when going from undoped to doped samples, indicates a change in the stoichiometry of the crystallized GST phase towards an Sb-rich GST phase (i.e. increased Sb-to-Te ratio ). Raman analyses confirmed the increase of Sb content in the segregated phase, given the observed shift in the Sb-Te feature. This is consistent with the early appearance of the hexagonal GST phase in doped samples, as previously observed in Sb-rich GST alloys [3], which are known for their high crystal growth rate and reduced grain boundaries, which could lead to reduced structural relaxation phenomena. The higher amorphous resistivity and the likely formation of an Sb-rich GST phase make doped Ge-rich GST alloys a valuable option for next-generation of PCM devices with both increased resistivity window and improved crystallization kinetics. [1] Cappelletti et al., "Phase change memory for automotive grade embedded NVM applications", J. Phys. D: Appl. Phys., vol. 53, n o 19, p. 193002, 2020. [2] Zuliani et al., "Overcoming Temperature Limitations in Phase Change Memories With Optimized Ge x Sb y Te z ", IEEE Trans. Electron Devices, vol. 60, n o 12, p. 4020-4026, 2013. [3] Daoudi et al., "The effects of Sb/Te ratio on crystallization kinetics in Ge-rich GeSbTe phase-change materials", Journal of Applied Physics, vol. 136, n o 15, p. 155105, 2024. Figure 1

Ge-rich Ge-Sb-Te alloy is a good candidate for future automotive applications due to its high crystallization temperature, which allows good data retention at elevated temperatures. Crystallization in this material is governed by elemental segregation which is key to thermal stability and device performance. In this work, elemental (Ge, Sb, Te) segregation is studied in situ during thermal annealing of Ge-rich Ge-Sb-Te thin films using X-ray fluorescence microscopy at ID16B beamline of ESRF with a beam size of 50 nm. Spatially resolved maps of Ge, Te, and Sb fluorescence yield are monitored and statistically analyzed as a function of temperature/time. In all investigated samples Sb appears to segregate much less than Te and Ge, indicating a lower mobility of this element. In situ, fluorescence mapping of samples doped with different amounts of carbon by ion implantation shows that carbon delays Ge and Te segregation to higher temperatures. Comparison with crystallization kinetics monitored by X-ray diffraction shows a good correlation between the occurrence of spatially resolved chemical inhomogeneities and the appearance of crystallized phases. This article discusses the dynamics of phase segregation in Ge-rich GST thin films monitored by synchrotron X-ray fluorescence. As Ge-rich GeSbTe is a good candidate for future automotive applications in phase change memories, understanding its crystallization kinetics and elemental dynamics is key to improving the performance of phase change materials.image (c) 2024 WILEY-VCH GmbH

Doped GeSbTe (GST)-based phase change materials are of growing interest due to their ability to enable high-temperature data retention for embedded memory applications. This functionality is achieved through Ge enrichment and addition of dopants such as N and C in stoichiometries such as GST-225, which improve the crystallization temperature and thermal phase stability. In this study, we examine the effect of these dopants on thermal conductivity using Raman thermometry. We report the temperature-dependent thermal conductivity of the amorphous and crystalline phases of Ge-rich GeSbTe (GGST) and Ge-rich GeSbTe N-doped (GGSTN) thin films. The results reveal a surprising temperature dependence of the thermal conductivity of the crystalline phase of GGST and GGSTN, a phenomenon not typically observed for GST-based materials. Additionally, enrichment of Ge and subsequent N-doping result in reduced thermal conductivity, which can benefit the power consumption of phase change memories. From a characterization perspective, Raman thermometry has been developed as a technique for simultaneous structural and thermal characterization of GST-based materials.

In this paper, we discuss a new development of 40nm SONOS eSTM™ (embedded Select in Trench Memory). We present an experimental study based on hot carrier injection mechanism for both programming/erase operations, performed on this new eNVM architecture. The optimization of drain and select gate biases, in order to define the programming and erasing threshold voltages, is also detailed. All the characterizations have been carried out for two different SONOS eSTM™ architectures giving an opportunity to propose different solutions. One of this using a continuous silicon nitride layer for two neighbour cells, taking advantage on the discrete charge trapping nature. As well, we performed endurance tests up to one million cycles for both architectures to evaluate the memory endurance.

We propose a physical model of complementary resistive switching (CRS) based on the disruption and reformation process of a metallic filament inside each Oxyde Resistive Random Access Memory (OxRRAM) composing the CRS. The driving forces involved in this process are electromigration forces, electron phonon coupling and joule heating. The model accounts well for the experimental CRS current voltage characteristics. The stability of the CRS states and the CRS operation in pulse regime, including the current and voltage peaks generation are discussed.

A clear comparison between Atomic Layer Deposition and Ion Implantation Si doping techniques is established. Comparable remnant polarization and coercive fields are obtained at lower Si content (%Si) for Ion Implantation, with a slight decrease of endurance performance. Switching signal engineering demonstrates a wide range of performance achievable with HfO 2 :Si ferroelectric layer.

This paper presents the fabrication, together with morphological and electrical characterizations of complementary resistive switches using the nanodamascene process. The as-fabricated devices are fully embedded in an insulating oxide, opening the way for further process steps such as three-dimensional monolithic integration. Complementary resistive switches electrical performance is consistent with resistive random access memories fabricated and characterized with the same procedure that showed ${R_{{\rm{OFF}}}}/{R_{{\rm{ON}}}}$ ratios of 100. Complementary operating voltages of ${V_{{\rm{th}}{\text{1,3}}}} = | \text{0.8} |\;{\text{V}}$ and ${V_{{\rm{th}}{\text{2.4}}}} = | \text{1.1} |\;{\text{V}}$ are obtained for 88 × 22 nm2 junction with a 6 nm thick HfO$_x$ junction.

We present a versatile nanodamascene process for the realization of low-power nanoelectronic devices with different oxide junctions. With this process we have fabricated metal/insulator/metal junctions, metallic single electron transistors, silicon tunnel field effect transistors, and planar resistive memories. These devices do exploit one or two nanometric-scale tunnel oxide junctions based on TiO 2 , SiO 2 , HfO 2 , Al 2 O 3 , or a combination of those. Because the nanodamascene technology involves processing temperatures lower than 300°C, this technology is fully compatible with CMOS back-end-of-line and is used for monolithic 3D integration.

Embedded flash memories having high-k metal gate-based logic devices will require modifications to the flash cells in order to remain economically feasible. One potential integration scheme is to keep the traditional ONO layer as the flash cell's inter-gate dielectric and replace its poly-Si control gate with the same high-k metal gate stack used for the logic devices. Preliminary electrical tests show that an HfSiON/TiN/a-Si gate stack does not significantly impact the EOT or leakage properties of the ONO layer. This stack is more robust than the traditional ONO with a poly-Si gate.

The silicon dioxide/silicon nitride/silicon dioxide (ONO) inter-gate dielectric layer has long been used in floating gate flash memories to provide coupling with the control gate, while simultaneously blocking leakage to it. Given the thickness and quality of the ONO, it is not possible to directly measure the leakage currents at low electric fields. This article presents the Oxide Stress Separation (OSS) technique which places a flash cell in a condition where the potential drop occurs entirely across the ONO. This allows for the measurement of currents on the order of 10−23A to be measured at low electric fields using nominal floating gate flash memory cells. Using OSS, state-of-the-art 40nm embedded-flash memories are characterized, allowing an evaluation of data retention contributors. Comparing OSS results with bake tests, ONO is found to be minimally responsible for the data retention drift, even in modern memories.

In this paper the memory performances of the TiN/HfO 2 /Ti/TiN and TiN/Ta 2 O 5 /TaOx/TiN memory stacks are compared. First, the bipolar switching parameters and the effect of the compliance current on the memory window and endurance are investigated. Then, the endurance and data retention properties are compared at a given operating current (100μA). Ta 2 O 5 based memory stack exhibits a better memory window (2 decades) and data retention, while the HfO 2 one shows good endurance properties (10 8 cycles). Finally, thanks to ab initio calculations using Density Functional Theory, the stability of the conductive filament is investigated in both HfO x and TaO x dielectrics.

In this article, the reliability of HfO2-based RRAM devices integrated in an advanced 28nm CMOS 16kbit demonstrator is presented. In order to improve the memory performance, a thin Al2O3 layer is inserted in the HfO2-based memory stack (TiN/Ti/HfO2/Al2O3/TiN). Thanks to extensive electrical characterizations on both single layer HfO2 and bilayer HfO2/Al2O3 memory stacks at device and array levels, the potential of the bilayer is put forward. From the experimental results, the thin Al2O3 layer has allowed to improve the endurance (memory window of about one decade after 1M cycles) and data retention (both the low and the high resistance states are stable after 6h at 200°C). Finally, thanks to our 3D model based on calculation of the Conductive Filament resistance using trap assisted tunneling (TAT) the role of Al2O3 as series resistance is highlighted.