We report on semi-metallic cobalt monosilicide (CoSi) as a CMOS-compatible thermoelectric (TE) material and discuss the effect of n- and p-type dopants on its transport properties. Thin films of CoSi are developed using chemical vapor deposition tools and subsequent rapid thermal processing. Film properties such as microstructure, crystallinity and elemental distribution are studied via electron microscopy, X-ray diffraction and time-of-flight secondary ion mass spectroscopy. Doping silicon with boron prior to silicidation impedes the Co-Si diffusion process, while phosphorus atoms distribute uniformly in silicides with no voids or agglomerations. CoSi makes a suitable n-type TE candidate and provides an alternative to Si or SiGe materials. Transport properties of undoped CoSi exhibit a linear dependence within the investigated temperature window, whereas dopants in CoSi increase the number of electron carriers that contribute to charge transport and thereby influence the Seebeck coefficient. Thus, TE characteristics of thin CoSi films can be tuned via (i) the type of dopants used and/or (ii) varying the residual silicon thickness post silicidation.

Fully functional pyroelectric films are fabricated on a silicon substrate with deep-trench structures, for the first time. Future integrated pyroelectric applications such as infrared sensors, energy harvesters or temperature manipulation devices require large current responses at low device footprints. In this work, pyroelectric Si-doped HfO 2 is deposited in trench structures to considerably increase the pyroelectric response, yielding a coefficient of f $\\pmb{p=-1560\\mu}\\mathbf{C}/\\mathbf{m}^{2}\\mathbf{K}$ , which is four times larger than that of PZT projected to the device area. A large harvestable energy density of $\\pmb{F_{\\mathbf{E}}=542} \\mathbf{J}/\\mathbf{m}^{3}\\mathbf{K}^{2}$ is measured. Simultaneously, CMOS compatible and RoHS compliant manufacturing is demonstrated. Metalorganic atomic layer deposition (ALD) is used to coat the $\\pmb{1:16}$ aspect ratio structures conformally with uniform silicon dopant levels.

We report the integration of a ferroelectric (FE) silicon-doped hafnium oxide material in ferroelectric field-effect transistor (FeFET) devices fabricated with an optimized interfacial layer in a gate-first scheme. The effect of increasing the permittivity (k) value of the interface layer on the performance of the metal–ferroelectric–insulator–semiconductor (MFIS)-FE-HfO 2 FeFET is studied in terms of its switching characteristics, endurance, and retention. In contrast to the previous work, the FE Si:HfO 2 -integrated FeFET devices show a low-power operation capability as well as an improved endurance characteristics without jeopardizing high-temperature retention. The utilization of an optimized SiON interface layer for MFIS-HfO 2 FeFET stack is discussed, and the improvements are outlined with reference to a standard low-k SiO 2 interface.

The recent discovery of ferroelectricity in thin film HfO2 materials renewed the interest in ferroelectric FET (FeFET) as an emerging nonvolatile memory providing a potential high speed and low power Flash alternative. Here, we report more insight into FeFET performance by integrating two types of ferroelectric (FE) materials and varying their properties. By varying the material type [HfO2 (HSO) versus hafnium zirconium oxide (HZO)], optimum content (Si doping/mixture ratio), and film thickness, a material relation to FeFET device physics is concluded. As for the material type, an improved FeFET performance is observed for HZO integration with memory window (MW) comparable to theoretical values. For different Si contents, the HSO based FeFET exhibited a MW trend with different stabilized phases. Similarly, the HZO FeFET shows MW dependence on the Hf:Zr mixture ratio. A maximized MW is obtained with cycle ratios of 16:1 (HfO2:Si) and 1:1 (Hf:Zr) as measured on HSO and HZO based FeFETs, respectively. The thickness variation shows a trend of increasing MW with the increased FE layer thickness confirming early theoretical predictions. The FeFET material aspects and stack physics are discussed with insight into the interplay factors, while optimum FE material parameters are outlined in relation to performance.

ZrO2-based metal-insulator-metal (MIM) capacitors are manufactured using atomic layer deposition. The impact of aluminum doping at the electrode interface on the electrical characteristics is evaluated using I-V, C-V and time dependent dielectric breakdown measurements. The aluminum doping profiles are examined using ToF-SIMS. Further, the impact of electrical stress and temperature on the C-V characteristic is analyzed. Experimental results indicate that charge trapping at the electrode vicinity is responsible for capacitance degradation effects. The incorporation of aluminum has a positive effect on breakdown voltage, lifetime, capacitance stability, and suppresses the formation of hysteresis effects.

In the semiconductor industry Germanium is expected as the promising channel material for future high-mobility CMOS transistors because of its highest hole mobility among common elemental and compound semiconductors, and an electron mobility that is two times larger than that of Si. This article shows that oxides can be grown and/or in a subsequent process step nitridized for planar Ge and Si devices at very low temperatures (T < 460 °C). The stable oxide growth on Germanium through plasma processing is studied as a function of relevant processing parameters like time, gaseous ambient etc. For Silicon the bonding structure of pure and nitridized low-temperature grown SiO2 is analyzed, followed by an electrical characterization of 0.8 to 1.2 nm interfacial layers on Si.

Ferroelectric properties in hafnium oxide based thin films have recovered the scaling potential for ferroelectric memories due to their ultra-thin-film- and CMOS-compatibility. However, the variety of physical phenomena connected to ferroelectricity allows a wider range of applications for these materials than ferroelectric memory. Especially mixed HfxZr1-xO2 thin films exhibit a broad compositional range of ferroelectric phase stability and provide the possibility to tailor material properties for multiple applications. Here it is shown that the limited thermal stability and thick-film capability of HfxZr1-xO2 can be overcome by a laminated approach using alumina interlayers.

Oxidation is a key process step in semiconductor device fabrication. Oxides are widely used in the production process as gate dielectrics, interfacial layers for high-k deposition, pad oxides, sacrificial oxides, screen oxides, protection oxides etc. Even though the used oxide thicknesses become thinner the thermal budget (roughly time at temperature) is generally not scalable with the thickness decrease due to the thermally activated oxidation process. However, for future sub-22 nm device structures a continuous reduction of oxidation temperatures is required to minimize dopant redistribution or deactivation, boron depletion, and oxidant enhanced diffusion effects. At the same time physical, chemical and electrical oxide quality has to be maintained. This is valid also for all process steps after device formation where high quality oxides are needed. BEOL applications like surface conditioning by oxidation is only one example. In this contribution we show that oxides can be grown and/or in a subsequent process step nitridized with an excellent electrical quality for planar Si and Ge devices but also conformally on 3D Si devices at very low temperatures (T < 400 °C). First the oxide growth with or without subsequent nitridation as a multi-step process is studied as function of time, and gas ambient on silicon and germanium, second the electrical characteristics of these various films are demonstrated. In the industry Ge is expected as the promising channel material for future CMOS because of its highest hole mobility among common elemental and compound semiconductors, and an electron mobility that is two times larger than that of Si. Therefore it is important to show outstanding electrical results of the Ge passivation layers grown at very low temperatures.

The growing demand on small system solutions is driving the compression of many functions into small package outline. This requires sophisticated solutions to avoid external circuitry area when integrating passive components. Moreover, decoupling capacitors need to be placed as close as possible to the active circuits in order to suppress cross-coupling between different power planes efficiently.In our paper we present the concept, fabrication and characterization results of ultra-thin silicon capacitors that can be integrated into chip package or embedded in PCB. High capacitance densities are achieved by using high-k materials as dielectric supporting a broad application range from RF-filtering to decoupling and energy buffering. Based on characterization results of voltage and temperature characteristics it is shown that this concept offers good electrical properties and linearity compared to conventional ceramic capacitors, like MLCC. Further, potential integration options are discussed showing the way to even thinner substrates down to 30 mu m.

System on chip (SoC) embedded memory solutions promise small form factors and high operating speed, as well as a high energy and cost efficiency. Single cell scalability and basic memory parameters such as data retention, cycling endurance and disturb characteristics on array level are important aspects in stand-alone memory development and can serve as a guideline for embedded solutions. However, one of the key aspects in embedded memory development is compatibility of the memory technology to its underlying complementary metal oxide semiconductor (CMOS) platform. This includes the voltage requirements for logic and memory operation, the need for additional lithographic steps and minimally CMOS invasive integration efforts, as well as the introduction of new materials and related contamination concerns. Especially in state of the art high-k metal gate (HKMG) CMOS technologies at minimum feature size (F) these aspects proof rather challenging when searching for a suitable embedded memory solution. As a consequence most approaches result in large memory cells of multiple F2 or leave a BEoL integration of the memory cell as the only viable option. With the introduction of ferroelectric hafnium oxide, however, a scalable one-transistor (1T) memory solution derived from the conventional HKMG transistor was presented for the 2X nm node. The therewith close resemblance of the memory and logic transistor appears ideally suited for combining nonvolatile data storage and logic circuitry on the same chip. Nevertheless, in order to fulfill these expectations and to ease manufacturing issues this resemblance has to be as close as possible. In the context of a minimally invasive memory integration strategy this means that ideally the ferroelectric hafnium oxide based memory transistor has to adapt to the HKMG transistor in terms of thermal budget and post treatments, vertical and lateral dimensions, the use of stress engineering, as well as metal gate and work function engineering. Based on experimental gate first transistor and metal insulator metal (MIM) capacitor data these aspects together with embedded memory requirements will be analyzed and critically discussed.

Ferroelectric hafnium oxide based systems have emerged as a new class of CMOS-compatible, scalable, 3D-capable and lead-free ferroelectrics striving to renew the scaling potential of ferroelectric memories. However, considering the multitude of unique physical characteristics provided by ferroelectrics and the industrial acceptance of HfO2 and ZrO2 based systems a much broader application space can be envisioned. Especially ferroelectric HfO2-ZrO2 thin films and its laminates with Al2O3 provide the flexibility and manufacturability required for an application specific tailoring of material properties.

We demonstrate the deposition of SixNy thin films using octachlorotrisilane (Si3Cl8) and ammonia between 300 and 500°C by an atomic layer deposition-like growth mechanism. Although there are chemical vapor deposition growth mechanisms present, which lead to an incomplete saturation, a step coverage >80% in high aspect ratio (>60:1) trenches could be achieved. The deposited films oxidize after contact with ambient air leading to substoichiometric N/Si ratios. Increasing the deposition temperature diminishes this oxidation. At temperatures >390°C a bulk N/Si ratio of ~1.3 is achieved. The capacitance–voltage (C–V) measurements of these films yield a k value of ~6 and a strong C–V hysteresis indicates significant charge trapping.

In this paper three different ZrO 2 ALD processes are studied as high-k dielectric in BEoL device applications. One metal organic precursor is compared to a halide precursor used with two different oxidizing agents. The structure, composition and morphology of the films are analyzed on bare Si wafers and the electrical properties such as capacitance, leakage and reliability are investigated on fully integrated BEoL decoupling capacitors. One of the halide ALD processes is identified as the most promising candidate for BEoL capacitor applications.

Aiming for future nonvolatile memory applications the fabrication and electrical characterization of 3-dimensional trench capacitors based on ferroelectric HfO2 is reported. It will be shown that the ferroelectric properties of Al-doped HfO2 ultrathin films are preserved when integrated into 3-dimensional geometries. The Al:HfO2 thin films were deposited by ALD and electrical data were collected on trench capacitor arrays with a trench count up to 100k. Stable ferroelectric switching behavior was observed for all trench arrays fabricated and only minimal remanent polarization loss with increasing 3-dimensional area gain was observed. In addition these arrays were found to withstand 2 *109 endurance cycles at saturated hysteresis loops. With these report the 3D capability of ferroelectric HfO2 is confirmed and for the first time a feasible solution for the vertical integration of ferroelectric 1T/1C as well as 1T memories is presented.

In this paper the potential of hafnium oxide as a CMOS-compatible ferroelectric for future memory applications is assessed. The high coercive field strength of ferroelectric hafnium oxide is identified as a key parameter being crucial to device performance. It provides the unique thickness and lateral scaling potential of this novel ferroelectric, while at the same time compromises its endurance properties due to large switching fields. Considering the ambivalent nature of this parameter as well as the emerging trade-off between retention and endurance, voltage controlled operation modes and different device concepts for ferroelectric hafnium oxide are discussed.

In this paper the potential of hafnium oxide as a CMOS-compatible ferroelectric for future memory applications is assessed. The high coercive field strength of ferroelectric hafnium oxide is identified as a key parameter being crucial to device performance. It provides the unique thickness and lateral scaling potential of this novel ferroelectric, while at the same time compromises its endurance properties due to large switching fields. Considering the ambivalent nature of this parameter as well as the emerging trade-off between retention and endurance, voltage controlled operation modes and different device concepts for ferroelectric hafnium oxide are discussed.

With the ability to engineer ferroelectricity in HfO 2 thin films, manufacturable and highly scaled MFM capacitors and MFIS-FETs can be implemented into a CMOS-environment. NVM properties of the resulting devices are discussed and contrasted to existing perovskite based FRAM.

ZrO2 is of very high interest for various applications in semiconductor industry especially as high-k dielectric in metal–insulator–metal (MIM) capacitor devices. Further improvement of deposition processes, of material properties, and of integration schemes is essential in order to meet the strict requirements of future devices. In this paper, the authors describe a solution to solve one of the key challenges by reducing the process time of the bottle neck high-k atomic layer deposition (ALD). The authors extensively optimized the most common ALD process used for the ZrO2 deposition (TEMAZ/O3) resulting now in a doubled growth rate compared to the published growth rates of maximum 1 Å/cycle. Chemical reactions explaining the origin of the high growth rate are proposed by theoretical process modelling. At the same time, the outstanding electrical properties of ZrO2 thin films could be preserved. Finally, the integration of the ZrO2 process in MIM capacitor devices with TiN electrodes was evaluated. Thereby, the known effect of TiN bottom electrode oxidation by the O3 process was analyzed and significantly reduced by different integration approaches including wet chemical treatments and ALD process variations. The resulting MIM capacitors show low leakage current and high polarity symmetry.