The local crystal phase and orientation of ferroelectric grains inside TiN/Hf0.5Zr0.5O2/TiN have been studied by the analysis of the local electron beam scattering Kikuchi patterns, recorded in transmission. Evidence was found that the ferroelectric phase of the layers is derived from an orthorhombic phase, most likely of space group Pca21. The orientation analysis reveals a strong out-of-plane texture of the polycrystalline film which is in accordance with a high remanent polarization Pr observed for P-V measurements. The results of this analysis help us to further optimize the ratio of ferroelectric grains and their orientation for many applications, e.g., in the field of emerging memory or infrared sensors.

We report 1-3 bit/cell FeFET operation through optimized HSO and HZO ferroelectric laminate layers using alumina interlayers. Memory window up to 3.5V, switching speed of 300ns, 10 years retention, and 10 4 endurance are reported. The gate stack lamination merits are discussed with insight potential of FeFET as an MLC memory.

In this paper, we give a perspective and recent overview of the emerging memory FeFET by shading the light on different aspects of the memory operation. The key fundamental questions related to material development, device scalability effects, utilization as multi-bit storage, write conditions, and memory endurance capability are overviewed based on experimental results of the MFIS based FeFET. The opportunities and challenges for the FeFET memory are discussed with emphasis on the fundamental principles and dependencies shaping its development.

We report for the first time the integration of silicon-doped hafnium oxide (HSO) antiferroelectric (AFE) material for enhanced floating-gate Flash memory speed by means of field-enhanced AFE polarization switching. An analytical description of the metal–ferroelectric–metal–insulator–semiconductor (MFMIS) stack physics during a write operation is introduced to study the effect of different stack optimization parameters on the interfacial oxide field. This, in turn, suggests different optimization routes for a ferroelectric field-effect transistor (FeFET) and Flash memories with a possible improved Flash interfacial field by AFE material integration. Improved Fowler–Nordheim tunneling based Flash speed of 300 ns is illustrated for the integrated devices. The theory and experiment of the MFMIS stack physics are discussed with emphasis on the role of stack parameters for optimized memory operation.

We report the integration of a ferroelectric (FE) silicon-doped hafnium oxide material in ferroelectric field-effect transistor (FeFET) devices fabricated with an optimized interfacial layer in a gate-first scheme. The effect of increasing the permittivity (k) value of the interface layer on the performance of the metal–ferroelectric–insulator–semiconductor (MFIS)-FE-HfO 2 FeFET is studied in terms of its switching characteristics, endurance, and retention. In contrast to the previous work, the FE Si:HfO 2 -integrated FeFET devices show a low-power operation capability as well as an improved endurance characteristics without jeopardizing high-temperature retention. The utilization of an optimized SiON interface layer for MFIS-HfO 2 FeFET stack is discussed, and the improvements are outlined with reference to a standard low-k SiO 2 interface.

The recent discovery of ferroelectricity in thin film HfO2 materials renewed the interest in ferroelectric FET (FeFET) as an emerging nonvolatile memory providing a potential high speed and low power Flash alternative. Here, we report more insight into FeFET performance by integrating two types of ferroelectric (FE) materials and varying their properties. By varying the material type [HfO2 (HSO) versus hafnium zirconium oxide (HZO)], optimum content (Si doping/mixture ratio), and film thickness, a material relation to FeFET device physics is concluded. As for the material type, an improved FeFET performance is observed for HZO integration with memory window (MW) comparable to theoretical values. For different Si contents, the HSO based FeFET exhibited a MW trend with different stabilized phases. Similarly, the HZO FeFET shows MW dependence on the Hf:Zr mixture ratio. A maximized MW is obtained with cycle ratios of 16:1 (HfO2:Si) and 1:1 (Hf:Zr) as measured on HSO and HZO based FeFETs, respectively. The thickness variation shows a trend of increasing MW with the increased FE layer thickness confirming early theoretical predictions. The FeFET material aspects and stack physics are discussed with insight into the interplay factors, while optimum FE material parameters are outlined in relation to performance.

We show the implementation of a ferroelectric field effect transistor (FeFET) based eNVM solution into a leading edge 22nm FDSOI CMOS technology. Memory windows of 1.5 V are demonstrated in aggressively scaled FeFET cells with an area as small as 0.025 μm 2 At this point program/erase endurance cycles up to 10 5 are supported. Complex pattern are written into 32 MBit arrays using ultrafast program/erase pulses in a 10 ns range at 4.2 V. High temperature retention up to 300 °C is achieved. It makes FeFET based eNVM a viable choice for overall low-cost and low-power IoT applications in 22nm and beyond technology nodes.

We present results of a non‐contact, real‐time feedback corona‐Kelvin characterization of the ferroelectric properties of Si:HfO2 thin films. Measurements were performed on free dielectric surfaces. The method uses corona charging pulses coupled with Kelvin probe‐measured surface voltage and gives non‐contact QV and CV characteristics. Analogous to voltage biasing of metal‐insulator‐metal (MIM) capacitors, large corona charge biasing is found to provide an effective means for poling of the ferroelectric films. Subsequent small increment corona charging is used to acquire hysteresis loops and determine the coercive field and permittivity characteristics. Negative and positive coercive fields of about ±1.2 MV/cm for the 3.5 mol% Si film and ±1.0 MV/cm for the 4.6 mol% Si film were determined from the hysteresis loops. These findings were in agreement with MIM capacitor measurements on sister wafers. Non‐ferroelectric behavior was also confirmed for the 11.3 mol% Si film. Another strength of the corona‐Kelvin method is the ability to perform full wafer mapping to assess spatial non‐uniformities of important dielectric properties. Results of this work indicate a radial symmetry of ferroelectric film properties, such as the permittivity at the coercive field, that are consistent with processing conditions during the crystallization anneal.

The recent discovery of ferroelectricity in thin hafnium oxide films has led to a resurgence of interest in ferroelectric memory devices. Although both experimental and theoretical studies on this new ferroelectric system have been undertaken, much remains to be unveiled regarding its domain landscape and switching kinetics. Here we demonstrate that the switching of single domains can be directly observed in ultrascaled ferroelectric field effect transistors. Using models of ferroelectric domain nucleation we explain the time, field and temperature dependence of polarization reversal. A simple stochastic model is proposed as well, relating nucleation processes to the observed statistical switching behavior. Our results suggest novel opportunities for hafnium oxide based ferroelectrics in nonvolatile memory devices.

A compact nanoscale device emulating the functionality of biological synapses is an essential element for neuromorphic systems. Here we present for the first time a synapse based on a single ferroelectric FET (FeFET) integrated in a 28nm HKMG technology, having hafnium oxide as the ferroelectric and a resistive element in series. The gradual and non-volatile ferroelectric switching is exploited to mimic the synaptic weight. We demonstrate both the spike-timing dependent plasticity (STDP) and the signal transmission and discuss the effect of the spike properties and circuit design on STDP.

Doped hafnia ferroelectric layers with thicknesses from 3 to 8nm are integrated into state-of-the-art 14nm FinFET technology without any further process modification. Ferroelectric devices show improved subthreshold slope (as low as 54mV/dec) and I-dsat (up to 165% increase). C-V curves show slight ferroelectric hysteresis. For the first time, we show that ring oscillators with ferroelectric devices can operate at frequencies similar to regular dielectrics, while improved subthreshold slope reduces their active power. We also propose a model for ferroelectric MOSFETs that spans both negative (NCFET) and positive (PCFET) ferroelectric capacitance (C-FE) devices. By carefully designed capacitance matching ferroelectric devices can provide significant power savings without sacrificing the speed.

Since the demonstration of the ferroelectric properties in hafnium based oxides in 2011 there is large interest to such films for ferroelectric FET, memory, and other applications. Engineering of ferroelectricity in HfO 2 relies on doping and annealing. For Si-doped HfO 2 films, a top metal electrode capping layer is deposited prior to annealing which is shown to cause ferroelectric behavior. In this paper we present results of non-contact corona-Kelvin characterization of poling phenomena for ferroelectric Si:HfO 2 thin films. Measurements were performed on free dielectric surfaces. The method uses corona charging and Kelvin force probe measurements. Corona charging pulses are analogous to voltage biasing, except that no top electrode is needed. Corona charging enables biasing the Si:HfO 2 to a near coercive field where onset of poling occurs. Mapping of the surface voltage with a small diameter Kelvin force probe allows to quantify poling phenomena, its uniformity and degradation during repetitive switching (Fig. 1). These results are of importance for fundamental understanding of switching mechanisms of ferroelectric Si:HfO 2 films. Figure 1

We successfully implemented a one-transistor (1T) ferroelectric field effect transistor (FeFET) eNVM into a 28nm gate-first super low power (28SLP) CMOS technology platform using two additional structural masks. The electrical baseline properties remain the same for the FeFET integration and the JTAG-controlled 64 kbit memory shows clearly separated states. High temperature retention up to 250 °C is demonstrated and endurance up to 105 cycles was achieved. The FeFET unique properties make it the best candidate for eNVM solutions in sub-2x technologies for low-cost IoT applications.

ABSTRACT With the discovery of ferroelectric hafnium oxide (FE-HfO2), the ferroelectric field effect transistor (FeFET), a long-term contender for non-volatile data storage, has finally managed to scale to the 2× nm technology node. Here for the first time, we correlate the thickness dependent ferroelectric properties of Si:HfO2 with the memory characteristics of small (56 bit) FeFET arrays. First, an electrical and structural analysis of metal-ferroelectric-metal capacitors is given. Even though possessing room-temperature deposited top electrodes, TiN / Si:HfO2 (20 nm) / TiN capacitors are showing deteriorated polarization characteristics as compared to their 10 nm Si:HfO2 counterparts. This could be attributed to an increased monoclinic phase fraction, as indicated by small-signal capacitance voltage and grazing incidence X-ray diffraction measurements. Identical Si:HfO2 thin films with thicknesses of 10 nm and 20 nm respectively, were utilized in a 28 nm high-k metal-gate CMOS flow to form small FeFET memory arrays of AND architecture. After extracting the most suitable operating conditions from erase matrix, single cell evaluation was performed by standard VP/3 program and a novel VP/3 positive-source drain erase scheme. Array cells incorporating 10 nm Si:HfO2 films showed a maximum memory window of 1.03 V whereas cells incorporating 20 nm Si:HfO2 films could reach up to 1.57 V. Moreover, in accordance to the basic material properties, the previously observed increased monoclinic phase fraction in 20 nm Si:HfO2 thin films correlate well with a reduced number of functional FeFET cells.

The discovery of ferroelectricity in HfO2 and ZrO2 based dielectrics enabled the introduction of these materials in highly scalable non-volatile memory devices. Typical memory cells are using a capacitor or a transistor as the storage device. These scaled devices are sensitive to the local structure of the storage material, here the granularity of the dielectric doped HfO2 layer, varying the local ferroelectric properties. Detailed studies are conducted to correlate these structural properties to the electrical performance to further optimize the devices for future applications.

Ferroelectric properties in hafnium oxide based thin films have recovered the scaling potential for ferroelectric memories due to their ultra-thin-film- and CMOS-compatibility. However, the variety of physical phenomena connected to ferroelectricity allows a wider range of applications for these materials than ferroelectric memory. Especially mixed HfxZr1-xO2 thin films exhibit a broad compositional range of ferroelectric phase stability and provide the possibility to tailor material properties for multiple applications. Here it is shown that the limited thermal stability and thick-film capability of HfxZr1-xO2 can be overcome by a laminated approach using alumina interlayers.

In this paper potential strategies to overcome the endurance limitations of hafnium oxide based ferroelectric field effect transistors are discussed. These pathways are based on the assumption that the high interfacial field stress and the accompanying charge injection in the metal-ferroelectric-insulator-semiconductor gate stack are the dominant degradation mechanisms during program and erase operation. Three different approaches capable of lowering or eliminating the interfacial field stress are being assessed - lowering the electrical field stress induced by polarization reversal; utilizing low voltage sub-loop operation; altering the capacitive divider within the gate stack.

Presented within this paper is a study on thin La-doped ZrO 2 films used as dielectric material in decoupling capacitors in BEoL. The effect of combined atomic layer deposition processes and the integration concept of La are discussed with respect to capacitance density, leakage current, breakdown voltage and reliability. Physical characterization helps to understand the measured parameters. Overall, the La-doping is able to improve the breakdown voltage significantly without degrading reliability, but at the expense of increased capacitance density compared to undoped films.