This work presents a process to fabricate FinFETs in bulk silicon with advancements in critical fabrication steps such as STI trench oxide recess and adjustment of fin height. These steps are accomplished with the adoption of Siconi™ Selective Material Removal (SMR™) in the fabrication flow. FinFETs obtained with this new integration scheme were tested in a co-fabrication process flow proposed to integrate planar CMOS and FinFETs in the same wafer. Morphological and electrical results indicate perfectly filled trenches, better fin height control and bulk FinFET static performance similar to planar CMOS.

A model for work-function variability (WFV) based on grain orientation differences of the polycrystalline metal gate is proposed, and the impact of the WFV on device and circuit performance is investigated. The model predicts that the WFV will surpass random dopant fluctuation beyond the 22-nm technology node and become the dominant factor to significantly increase static RAM failure probabilities. The prediction is verified through experimental characterization and analysis.

The Implant-Free Quantum Well Field-Effect Transistor (FET) offers enhanced scalability in a planar architecture through the integration of heterostructures. The Implant-Free architecture fully utilizes the band offsets between different materials, whereby charge carriers are effectively confined to a thin channel layer. This prevents sub-surface source/drain leakage observed in classical bulk Metal-Oxide-Semiconductor FETs at small gate lengths. An investigation of the VT-tuning capabilities of this technology reveals sensitivity to both well doping and bulk voltage.

This paper presents a TCAD study on the effectiveness of stress techniques on bulk FinFETs and planar nFETs, comparing gate-first to gate-last schemes. It will be shown that strained Contact Etch-Stop Layers (CESL) are less effective in narrow FinFETs than on planar FETs when a gate-first scheme is used. On the other hand, using a gate-last scheme significantly enhances CESL effectiveness both on FinFETs and planar FETs, especially when the device width is scaled. A tensile gate fill material leads to a completely different channel stress configuration in gate-last than in gate-first nFETs. While for gate-first, this leads to up to 10% mobility improvement for narrow-width FinFETs, a mobility degradation is predicted when tensile gates are used in a gate-last configuration. For this stressor, FinFETs show a different width dependence than planar FETs due to stresses in the fin sidewall, leading overall to higher mobilities in FinFETs than in their planar counterparts.

A technique is presented to study the electrostatic degradation of key germanium metal-oxide-semiconductor field-effect transistor (MOSFET) performance metrics such as the subthreshold slope SS, the drive current, and the OFF-state current. This is calculated using the superposition of the contributions from individual trap profiles, arising from a piecewise approximation of any arbitrary interface-trap spectrum. A technology computer-aided design simulation using this approach has been directly applied to the electrical evaluation of various scaled Ge p-channel FETs with different passivation schemes. The relative SS degradation due to interface traps is shown to be independent of the gate length, even in scaled devices exhibiting short-channel effects. Additionally, a linear dependence of the relative degradation with an equivalent oxide thickness (EOT) is observed. As such, a transistor's subthreshold performance is less impacted by a given concentration of interface traps, as the EOT is further reduced. Finally, the MOSFET drive current is shown to be degraded due to interface traps, mainly through additional scattering in the channel, while the electrostatic effect is rather small.

Millisecond laser annealing is used to fabricate ultra shallow arsenic junctions in preamorphized and crystalline germanium, with peak temperatures up to 900 degrees C. At this temperature, As indiffusion is observed while yielding an electrically active concentration up to 5.0 x 10(19) cm(-3) for a junction depth of 31 nm. Ge preamorphization and the consecutive solid phase epitaxial regrowth are shown to result in less diffusion and increased electrical activation. The recrystallization of the amorphized Ge layer during laser annealing is studied using transmission electron microscopy and spectroscopic ellipsometry. (C) 2010 The Electrochemical Society. [DOI: 10.1149/1.3512990] All rights reserved.

Flat band voltage (V-FB) roll-off in long channel devices at thin equivalent oxide thickness (EOT) is studied on SiO2/nitrided-HfSiO stacks. V-FB increases when SiO2 interfacial layer thickness decreases, and charges pumping (CP) frequency sweep analysis shows higher trap density near Si/SiO2 interface. Based on this observation, an atomic diffusion model is introduced. Higher concentration of nitrogen atom in the HfSiO(N) layer diffuses to the Si/SiO2 interface through the SiO2 layer in thinner SiO2 device, and accumulates near Si/SiO2 interface which can introduce higher density of interfacial traps. Lifetime extracted from negative bias temperature instability (NBTI), and mobility are also degraded in thinner SiO2 devices due to the higher interfacial trap density.The V-FB roll-off can be improved by lowering nitrogen concentration in the HfSiO(N) layer from optimizing plasma nitridation pressure, decreasing post deposition anneal temperature, or using defect absorbing layer on the high-k oxide. (C) 2011 Elsevier Ltd. All rights reserved.

Ge is one of the promising candidates for high-mobility channel material in future complementary metal-oxide-semiconductor technology. High-field transport in short-channel Ge p-channel field-effect transistors (PFETs) needs to be examined since device performance is determined by high-field velocity in quasi-ballistic transport regime. In this paper, ballisticity and the relationship between carrier velocity and mobility in short-channel (70-nm) Ge PFETs were thoroughly investigated. A 1.6 × -2× higher velocity was confirmed in Ge PFETs than that in Si PFETs. Uniaxial stress is also a strong performance booster besides high-mobility substrate. The effectiveness of the uniaxial stress to velocity enhancement in Ge PFETs was experimentally demonstrated in short channel regime. A 1.4× higher drive current can be achievable by uniaxially strained Ge PFET in ballistic transport regime as compared with strained Si PFET.

Extraction of interfacial trap density N-it in extremely reduced gate oxides with equivalent oxide thickness (EOT) below 1 nm by conventional charge pumping is virtually impossible due to the high gate leakage current through the very thin oxide. However, interface quality assessment in subnano EOT devices is essential for the reliability and performance improvement of future logic devices. In this paper, an accurate approach to determine the interfacial trap density in a 5.8-angstrom EOT device is performed by an advanced charge pumping technique employing ring-oscillator-connected devices. A consistency comparison of this technique to the conventional charge pumping is done by a frequency sweep on the 10.1-angstrom EOT device. Clear charge pumping currents are obtained on the 5.8-angstrom EOT oxide, and further analysis by varying the applied frequency and amplitude is performed. The interface trap density in the 5.8-angstrom EOT device is found to be higher than that in the 10.1-angstrom EOT device due to the physically reduced interfacial layer in the thinner EOT device. Moreover, direct tunneling-based calculation gives the charge injection distance as about 2 angstrom inside the oxide. Stress-induced defect generation is investigated by applying dc stress between charge pumping and I-drain-V-gate measurements. The 5.8-angstrom EOT device shows higher initial N-it but lower stress-induced N-it as compared with the 10.1-angstrom EOT device. The bulk trap N-ot generated after stress is higher in the 5.8-angstrom EOT device due to the higher initial bulk trap density.

Through a combination of electrical measurements, technology computer-aided design simulations, and wafer bending experiments, the effect of elastic stress relaxation on the layout dependence of Si 1-x Ge x -channel p-channel field-effect transistors (pFETs) is studied. This work focuses on scaling of the transistor width W , the active-area length (length of diffusion, LOD) for isolated transistors, and poly-to-poly length L P/P of nested configurations. A strong narrow-width current enhancement is reported, even for relatively large widths, above 100 nm. On the other hand, the layout dependence on LOD or L P/P is also predicted but only for aggressively scaled layouts (LOD or L P/P below 100 nm). W and L P/P scaling lead to current enhancement, whereas LOD scaling is expected to degrade performance. No significant dependence of short-channel threshold voltage on W , LOD, or L P/P was observed. This study indicates that, as higher germanium concentrations of the channel lead to more layout dependence, this concentration may need to be optimized carefully to combine high channel mobility with limited added design complexity. Moreover, the channel thickness should be kept as thin as possible, as layout dependence is enhanced for thicker channels.

FinFET devices are expected to be appropriate candidates for further scaling down logic devices while maintaining short-channel effects under control [1] [2] [3]. In this work, two different characterization methods are used to evaluate the impact of device characteristic dimensions such as the fin height and width on variability and performance. Both techniques can accurately predict the physical dimensions but the current-based method was shown to be more in line with the actual physical profiles. The results have been validated by cross-sectional transmission electron microscopy (TEM), confirming the within wafer variations.

EXECUTIVE OVERVIEW The computation and storage capabilities that will be expected from future ICs and systems require that we go on scaling. Because we are closing in on the physical limits of IC scaling, we have to push the technology to the extreme. That is why we are developing new transistor architectures and introducing new materials and processing techniques. Our goal is to develop processes that can be used in high-volume manufacturing of future logic and memory ICs. In our R&D into logic ICs and peripheral DRAM, we follow two tracks. One is refining established technologies for the next generation of ICs, and a second is exploring and developing the options for further generations.

Recent developments on CMOS-driven III-V and Ge MOS (Metal-oxide-semiconductor) technologies provide new opportunities in advancing the performance envelope of MOS device as well as the relevant electrical characterization techniques. Understanding the capacitance-voltage (CV) and conductance voltage (GV) responses of the III-V/Ge MOS devices can lead to better assessments of the oxide-semiconductor material systems and more accurate performance predictions.

The reliability of 0.69 nm EOT GdHfO dielectric with metal gate is investigated. The threshold voltage shift at identical PBTI stress conditions is only 20% of the shift of a 0.78 nm EOT HfO2 + La2O3 (or HfLaO) device. The resulting reliable gate over-drive at 10 years of this GdHfO device is 0.85 V. Analysis of the stress induced leakage current (SILC) shows that the improved PBTI in the GdHfO device is related to the reduced trap generation under low bias stress, which already exists in the HfLaO device. (C) 2011 Elsevier Ltd. All rights reserved.

In this work we explore several doping schemes for aggressively scaled multi-gate field-effect transistor devices with the conduction channels wrapped around silicon fins (FinFETs) (H Fin∼37 nm, W Fin≥10 nm, L g≥30 nm), using conventional ion implantation (I/I), and suitable for both logic and dense circuit applications. We demonstrate that low-energy and: 1) low-tilt, double-sided extension(-less) I/I, or 2) high-tilt, single-sided extension I/I schemes can enable pitch scaling without resist shadowing effects, with no penalty in device performance and yielding higher six transistors-static random access memory (6T-SRAM) static noise margin (SNM) values. Key advantages of the extension-less approach are: reduced cost and cycle time with 2 less critical I/I photos, enabling better quality, defect-free growth of Si-epitaxial raised source/drain (SEG), and up to 20× lower I OFF. It, however, requires a tight spacer critical dimension (CD) control, a less critical parameter for the single-sided I/I scheme, which also allows wider overlay margins.