The duration and interval of the input signal in two terminal memristor based reservoir systems is constrained by the decay time of a conventional memristor. Here, we demonstrate that the third terminal of a Solid Electrolyte $\text{ZnO}/\text{Ta}_{2}\mathrm{O}_{5}$ Thin-film Transistor (SE-FET) can be used to control the decay time by using a variable read voltage, without any additional circuit elements. Using this approach, we have benchmarked the performance of our SE-FET based RC system for a task of recognition of spoken digits with a high accuracy of 99.4%.
We optimized the structural parameters of the metasurface (MS) for enhanced bottom-emitting organic light-emitting diodes (B-OLEDs). MS consists of mixed metallic nanoslot arrays. The performance of MS-integrated B-OLED is estimated by out-coupling efficiency and reflection of the ambient light. The layer thicknesses of the capping layer and the MS which affect the excitation of surface plasmon are optimized and the width and length of nanoslot are determined by reducing reflectance caused by localized SP. The optimized metasurface enhances performances by 16% over the conventional B-OLED.
Practical quantum computers require coordinated operation on a large number of qubits $(\sim 10^{4})$, posing significant implementation challenges. In this paper, we summarize our recent work on scalable CMOS circuits to route control signals in a silicon MOS quantum dot spin qubit. We also present a cryogenic compact model enabling circuit design and simulation at cryogenic temperatures. The proposed design is an important step toward implementation of scalable solid-state quantum processors.
We address our recent activities on TiN/HfZrO2 (HZO)/TiN MFM capacitors, HZO/Si FeFETs for memory applications, and reservoir computing using HZO/Si FeFETs for AI applications. We have shown that MFM capacitors with 4-nm-thick HZO realizes low operating voltage and high read/write endurance. We have pointed out the importance of a large amount of electron traps in HZO on the FeFET memory characteristics. Also, we have demonstrated reservoir computing using FeFETs for applications of speech recognition.
Dynamic performance has been compared systematically among 3300V scaled IGBTs with scaling factor (k) from 1 to 10 by TCAD simulations. Even with much stronger Injection Enhancement (IE) effect, Dynamic Avalanche (DA) in scaled IGBTs is proven to be more suppressed than in $\mathrm{k}=1$ case, and it's demonstrated that IGBT scaling is able to break through the trade-off between lower on-state voltage drop and better switching controllability.
In this work, a thick HZO-based gate device is examined for memory applications owing to its wider memory window. The TiN-HZO-TiN film layers are demonstrated by measuring electrical properties such as polarization, capacitance, and current. In addition, to apply a thick HZO stack to an integrated memory device, we develop an MFMIS etching process and define a gate structure with a sufficient memory window of 4 V.
In this paper, a 16nm saddle fin structure was modeled. Active area width (AA CD), AA tapper angle, buried word line trench width (BW CD) and BW tapper angle effects on the device performance were investigated using a built-in drift-diffusion solver. Our analysis confirms that the smaller AA tapper angle and proper AA CD can generate higher on-state current (Ion) and lead to lower off-state current(Ioff). In addition, in our fin sputter model, lower sputter ratio increase Ion, and lower sputter angle reduce Ioff and subthreshold swing(SS).
Over the years, there has been much research on ferroelectric field-effect transistors (FeFETs) for memory applications. In this work, we propose a novel recessed channel FeFET with gate metal-ferroelectric $(\text{FE})-\text{metal}-\text{FE}-\text{metal}-\text{SiO}_{2}$ interlayer (IL)-silicon (MFMFMIS) gate stack, which is named a dual ferroelectric recessed channel FeFET (DF-RFeFET) aimed to increase the memory window (MW) for high-performance memory applications. With calibrated FE parameters and device models in technology computer-aided design (TCAD) simulation, we found that the DF-RFeFET can have a large MW of 3.2 V. In addition, guidelines for the DF-RFeFET design are provided in terms of the thickness ratio of the inner and outer FE layers to maximize the MW.
An experimental study of drain current statistical characteristics in two vertically stacked nanowire MOSFETs (bottom one: Omega shaped and top one: nanowire) is presented. The most critical parameter variations are identified using an advanced mismatch model that well describes the experimental results, while the impact of channel geometry is examined for every source of process variations.
We proposed a novel design of N-channel Reverse Conducting vertical IGBT (RC-VIGBT) with the N+ cathode partially covered with the lightly doped P layer in the embedded diode block. The snap-back effect can be effectively suppressed by this coverage with the buried P layer, and the switching energy loss can be reduced by introducing the P-/N+ injection control backside structure in the IGBT block. The proposed structure can be easily fabricated with only one additional mask compare with the conventional structure.
We present a new method for temperature distribution measurement with sub-100-nm spatial resolution using molecular modification on device surfaces. In this method, a Au nanosheet modified with self-assembled monolayers (SAM) is locally heated by Joule heating. The SAM molecules are desorbed due to the local heating, and the temperature is estimated from the molecular distribution evaluated by Kelvin probe force microscopy (KFM). The validity of the temperature estimation is confirmed by finite-element-analysis (FEA) results. This method is useful for visualizing thermal distribution in nanoscale devices such as metal nanosheet gas sensors.
We investigated metal-insulator-semiconductor (MIS) contact using $\mathbf{GaO}_{\mathrm{x}},\mathbf{TiO}_{\mathrm{x}}$ , and $\mathbf{ZnO}_{\mathrm{x}}$ on n- GaN having Si doping concentration of $\boldsymbol{2\times 10}^{18} \mathbf{cm}^{-3}$ . While we obtained the low specific contact resistivity $(\boldsymbol{\rho}_{c})$ of $\boldsymbol{7.1\times 10^{-7}\Omega}\cdot \mathbf{cm}^{2}$ with $\mathbf{GaO}_{\mathrm{x}}$ and $\boldsymbol{7.7\times 10}^{-5}$ Ω·cm 2 with $\mathbf{TiO}_{\mathrm{x},}\rho_c$ increased with $\mathbf{ZnO}_{\mathrm{x}}$ . We further evaluated the band alignment of oxide/GaN and discussed the variation of the Schottky barrier height (SBH) based on the metal-induced gap states (MIGS) model to validate our results.
Oxide interface charges is an important factor to be assessed in technology development especially for a trench-gated power device. The plasma reactive ion etching process is used to form highly vertical trenches whereby the oxide-silicon interface is often saturated by large amount of oxide interface charges. These charges are responsible for the device performance, stability, and long-term reliability degradation. In this work, we characterized the charges by performing various %H 2/ N 2 forming gas annealing in FS IGBT and determined the optimal anneal condition to intrinsically passivate the oxide interface charges.
This paper reports on the scalability of the new wurtzite-type ferroelectrics between 500 and 10 nm thickness by investigating $\mathrm{A}1_{1-\mathrm{x}}\text{Sc}_{\mathrm{x}}\mathrm{N}$ films. Unlike in most other ferroelectrics, no pronounced dependence between coercive field and film thickness was observed, therefore allowing operation below 3 V at 10 nm thickness. Together with our parallel success in fabricating the first wurtzite-type based Si FeFET, this is an important building block for developing advanced integrated electronic devices utilizing this novel material class.
We have theoretically investigated the operation mechanism of capacitive memory with metal-ferroel ectric-insulator-semiconductor (MFIS) structure by simulation. Since the large ratio of inversion and depletion capacitance of semiconductor, high $\mathrm{C}_{\text{HCS}}/\mathrm{C}_{\text{LCS}}$ can be achieved. Besides, multi-level cell operations are possible because of partial polarization switching. In addition, the role of doping concentration of n-type region $(\mathrm{N}_{\mathrm{D}})$ is explored. Lower N D results in higher $\mathrm{C}_{\text{HCS}}/\mathrm{C}_{\text{LCS}}$ due to the larger depletion width after erase.
A significantly high linearity was achieved by controlling oxygen vacancy in IGZO photonic-synaptic device. A substrate bias during sputtering process and subsequent nitrogen plasma treatment were used to control the oxygen vacancies in IGZO thin film. As the oxygen vacancies were reduced, the synaptic transistor mimics biological synapses. The nonlinear factor of weight update was considerably improved from 1.55 to 0.41, which is a sufficient level for highly accurate artificial neural network.
In this work, we report on ultra-thin InGaZnO (IGZO) thin film transistors (TFTs) with a channel thickness $(\mathrm{T}_{\text{ch}})$ ranging from 0.7 nm to 4.3 nm and a channel length $(\mathrm{L}_{\mathrm{c}\mathrm{h}})$ below 100 nm. These IGZO channels were derived by atomic-layer-deposition, with a high In atomic ratio of 92%. It is found that $\mathrm{T}_{\text{ch}}$ has a significant effect on the electron transport in the IGZO channel. Well behaved performance can be achieved for TFTs with $\mathrm{T}_{\text{ch}}$ between 1.5 nm and 3.5 nm. Gate bias stress stability test were also systematically studied on these IGZO TFTs under various gate biases. It is believed that the generation of donor-like traps possibly originating from ionized oxygen vacancy, in addition to electron (de)trapping could be the underlying mechanism. This study shows that IGZO TFTs could be highly promising for back-end -of-line (BEOL) applications.
A broadband noise measurement system is newly developed and demonstrated at temperatures between 3 K and 300 K. Using the system, wideband noise spectroscopy (WBNS) from 20 kHz to 500 MHz is carried out for the first time, revealing that shot noise is the dominant white noise down to 3 K. The paper also suggests, by means of WBNS, the possibility of extracting the baseline noise characteristics, which do not include the noise component that varies a great deal from device to device.
This invited paper reviews the recent development of all-inkjet-printed organic thin-film transistors for wearables, for which an amplifier with low power and high gain is essential for biosensors. The techniques to lower the operating voltages of printed organic transistors are discussed and summarized, by reducing the trap density within the devices. By operating the devices in the subthreshold regime, an amplifier demonstrates low power (< 1 nW) and high gain (260 V/V). With a strip-helix-fiber structure, the amplifier be potentially weaved into textiles for wearables.
