This interactive event will include several distinguished panelists representing a broad variety of career choices in the areas of start-ups, industry, research, and academia available to graduates in electrical and computer engineering. Following short introductory remarks by each panelist, this forum will open for audience interaction in which the audience is invited to express a broad range of questions to the panelists.

A Ternary neural network (TNN) based patient- specific single lead Electrocardiography (ECG) processor for the early detection of cardiac arrhythmias (CA) is presented. The designed system detects upward/downward turning points in the ECG to detect the slope variation and calculates the fiducial points of the PQRST beats, with high auto-patient adaptability. A 3-layer Feedforward Neural Network with ternary weights is integrated on the sensor to classify eight different types of Shockable CA (SCA) and non-SCA (NSCA) with sensitivity and specificity of 99.1% and 99.8% respectively. The proposed processor is also synthesized using 65nm CMOS technology having an area of 1.08 mm 2 with an overall power consumption of 2.52 μA, energy efficiency of 72 nJ/detection.

An ultra-low power ECG processor ASIC (application specific integrated circuit) with R-wave detection and data compression is presented, which is designed for the long-term implantable cardiac monitoring (ICM) device for arrhythmia diagnosis. An adaptive derivative-based detection algorithm with low computation overhead for potential arrhythmia recording is proposed to detect arrhythmia with the occasional abnormal heart beats. In order to save as much as possible cardiac information with the limited memory size available in the ICM device, a hierarchical data buffer structure is proposed which saves 3 types of data, including the raw ECG data segments of 2 seconds, compressed ECG data segments of 45 seconds, and R-peak values and interval lengths of >2000 beat cycles. A modified swinging-door-trending (SDT) method is proposed for the ECG data compression. The ASIC has been implemented based on fully-customized near-threshold standard cells using the thick-gate transistors in 65-nm CMOS technology for low dynamic power consumption and leakage. The ASIC core occupies a die area of 1.77 mm 2 . The measured total power is 2.63 μW, which is among the ECG processors with the lowest core power consumption. It exhibits a relatively high positive precision rate ( P + ) of 99.3% with a sensitivity of 98.2%, in contrast to the similar designs in literature with the same core power consumption level. Also, an ECG data compression ratio ( CR ) of up to 17.0 has been achieved, with a good trade-off between the compression efficiency and loss.

A full-customized electrocardiograph (ECG) processor for arrhythmia detection is proposed in this paper, which is composed of detection engine, circulated buffer, register bank and instruction/data interfaces. The processor, which is fed by 0.9-V parallel digitized ECG signals, generates stamp pulses of detected QRS-complexes and arrhythmia location by searching for local extremes of signal derivative with self-adaptive thresholds. The precision (Pre) and sensitivity (Sen) of the proposed algorithm are 99.1 % and 96.9 % respectively. The extra false positive (FP) rate of proposed ASIC-implemented ECG processor is extremely low even with power-line interference (PLI) of 0.0663 V-p and/or rail-to-rail baseline drift (R2R BLD). The processor stands out for its relatively low power consumption of 17.7 pJ/cycle with superior robustness to interferences compared to other designs in literature.

This paper presents a power-efficient, high dynamic range, high input impedance data acquisition circuit for an implantable electrocardiogram (ECG) detector in 65 nm CMOS, occupying an active area of 0.225 mm2. To enhance the dynamic range, we utilize a 3rd-order continuous-time sigma-delta modulator with a programmable input gain coefficient and an embedded antialiasing filter. The implementation of the non-inverting integrator allows a high input impedance for the ECG application. The measurement results show that it obtains 84.2dB SNDR in a 150Hz bandwidth with a 1V power supply, consuming 5.4μW at a nominal gain of 0dB. The maximum dynamic range is 99.3dB with the programmable gain activated from 0 to 18dB.

This paper presents an incremental analog-to-digital converter (IADC) with a two-phase linear-exponential accumulation loop. In the linear phase, the loop works as a first-order structure. The noise-coupling (NC) path is then enabled in the exponential phase thus boosting the signal-to-quantization-noise ratio (SQNR) exponentially with a few number of clock cycles. The two-phase scheme combines the advantages of the thermal noise suppression in the first-order IADC and SQNR boosting in the exponential mode. The uniform-exponential weight function allows the data weighted averaging (DWA) technique to work well, leading to the rotation of the multi-bit DAC mismatch error. Meanwhile, this scheme does not destroy the notches, which can be utilized to suppress the line noise. Implemented in 65-nm CMOS under 1.2-V supply, the analog-to-digital converter (ADC) achieves an signal-to-noise + distortion ratio (SNDR)/dynamic range (DR) of 100.8 dB/101.8 dB with 20-kHz bandwidth (BW), 550 $mu text{W}$ , and 0.134 mm 2 , resulting in Walden/Schreier FoM W /FoM S of 153 fJ/176.4 dB, respectively. The differential and integral nonlinearities are +0.27 LSB/−0.27 LSB and +0.84 LSB/−0.81 LSB, respectively.

This paper presents an incremental analog-to-digital converter (IADC) with a two-phase linear-exponential accumulation loop. In the linear phase, the loop works as a first-order structure. The noise-coupling (NC) path is then enabled in the exponential phase thus boosting the signal-to-quantization-noise ratio (SQNR) exponentially with a few number of clock cycles. The two-phase scheme combines the advantages of the thermal noise suppression in the first-order IADC and SQNR boosting in the exponential mode. The uniform-exponential weight function allows the data weighted averaging (DWA) technique to work well, leading to the rotation of the multi-bit DAC mismatch error. Meanwhile, this scheme does not destroy the notches, which can be utilized to suppress the line noise. Implemented in 65-nm CMOS under 1.2-V supply, the analog-to-digital converter (ADC) achieves an signal-to-noise + distortion ratio (SNDR)/dynamic range (DR) of 100.8 dB/101.8 dB with 20-kHz bandwidth (BW), 550 $\mu \text{W}$ , and 0.134 mm2, resulting in Walden/Schreier FoMW/FoMS of 153 fJ/176.4 dB, respectively. The differential and integral nonlinearities are +0.27 LSB/−0.27 LSB and +0.84 LSB/−0.81 LSB, respectively.

This paper presents a linear-exponential two-phase multi-bit incremental ADC (IADC). The exponential integration in the proposed IADC is generated by positively feedback the integrator output to the input, which can accumulate the signals stably due to the reset operation in IADC. To avoid the nonlinearity due to the signal-dependent charge injected from the reference, this work separates the sampling capacitor and the DAC capacitor. It will relax the requirement of reference buffer for fast-settling under a high sample rate. Then, we reconfigure the DAC capacitor to directly offer the exponential integration, resulting in saving in the usage of integration capacitor with a compact implementation. The linear-exponential two-phase scheme provides data-weighted-averaging-friendly weighting function to suppress the multi-bit DAC mismatch error. Fabricated in a 65nm CMOS under 1.2 V supply and clocked at 128MHz, the ADC achieves an SNDR/DR/SFDR of 86.02/94.6/103.03dB with 500kHz BW, 20mW & 0.26mm2, resulting in FoMs of 168.57dB.

Wireless power transfer (WPT) via inductive coupling is a convenient way to charge power-starved portable/wearable devices. Recently, device-to-device (D2D) wireless charging was demonstrated [1,2], which expands the range of WPT applications. Different from the traditional wireless charging, which obtains its energy from the AC mains and has virtually unlimited energy, the D2D charging sources power from an energy-constrained battery. Therefore, achieving the maximum-efficiency transfer is a key design issue. A zero-voltage-switching (ZVS) Classy receiver with maximum efficiency tracking, but using several off-chip passives, was designed in [1] to improve the rectifier and coupling-link efficiencies for unidirectional D2D wireless charging. In [2], a reconfigurable wireless-power transceiver (TRX) with the maximum-current charging mode was proposed to turn a WPT receiver (RX) into a WPT transmitter (TX) with negligible additional hardware, which enabled the bidirectional D2D wireless charging. However, the TX mode efficiency and maximum output power in [2] are relatively low, and its WPT distance is short.

A fully integrated single-input dual-output switched-capacitor converter with dynamic power-cell allocation for application processors is presented in this summary. The power cells can be dynamically allocated according to the loads, and the efficiency is improved by 4.8%. A dual-path voltage-control oscillator (VCO) that works independently of the power-cell allocation is proposed to achieve a fast and stable regulation loop. The converter achieved peak efficiency of 83.3% and maximum combined load-currents of 100mA while maintaining minimized cross regulation.

This paper presents two calibration schemes to correct the stage gain error in analog-to-digital converters. The two approaches target different scenarios, either better calibration accuracy or less digital overhead. First, we optimize the gain calculation scheme in the conventional code statistics-based approach, which improves the calibration accuracy. Moreover, we introduce a missing-code-detected calibration that replaces the calculation of the gain coefficient by counting and multiplying the number of missing codes in the digital domain, which significantly simplifies the digital implementation. To eliminate the calibration dependence on the input signal, we implement a testing signal generation on-chip. We also compare these calibration schemes with the requirements of the input signal, the calibration accuracy, as well as the hardware overhead based on a mathematical model with behavior simulations. Both concepts were verified in an 11-bit 80-MS/s successive approximation register with a bridge digital-to-analog converter fabricated in a 65-nm CMOS.

This paper presents a single-stage wireless charger using a current-mode active rectifier with accurate output current regulation for efficient wireless charging. As we know, the rectifier processes an AC input voltage/current and a pulsing output current which are difficult to be accurately sensed on chip with small area and power overheads. The proposed current sensing technique uses a replica sensing stage in parallel with the main power stage. It consists of two small cross-connected sensing PMOS transistors, a small filtering capacitor, and a dynamic replica load. In addition, by adaptively tuning the delay of the power NMOS driving signal, the charging current is regulated precisely. This single-stage wireless charger operates at 6.78MHz, and is designed in a 0.35μm CMOS process. Simulation results show a minimum 97.5% current regulation accuracy over a 10× (from 100mA to 1A) output-current range. The peak efficiency of 94% is achieved with 4.2W output power.

This paper presents a time-interleaved (TI) SAR ADC that utilizes the characteristic of the current integrating (CI) sampler for sampling time skew background calibration, while it also provides buffering and anti-aliasing filtering functions, simultaneously. The inter-sample interaction in the CI sampler enables the mapping of the time domain information to the amplitude domain. Time skew errors can therefore be extracted by comparing the output-code variance among channels without requiring a reference path. A 2-channel 2 GS/s 7b TI-SAR prototype realized in 28-nm CMOS achieves a 36.4 dB SNDR at Nyquist with >2.6 GHz ERBW after calibration. The ADC with CI sampler consumes 7.62 mW, leading to a Walden FoM of 70.8 fJ/conversion-step.

The measurement of the analog-to-digital converter (ADC) output by exciting the signal generator with a high precision input signal allows the determination of ADC's static characteristics using a histogram-based approach. However, this method exhibits some limitations imposed by the input signal, including its high resolution and high linearity that are causes for concern when testing a high precision ADC. Recent research work has been trying to overcome such limitations. Nonetheless, it is necessary to discover a simple and low-cost method to measure the linearity of a high precision ADC through a low precision stimulus. This paper introduces a novel procedure that allows the relaxation of the requirements of the signal source for estimating ADC's linearity characteristics. The proposed method requires two sets of testing sources, being both ramp signals, one of low-precision and the other attenuated. Simulation and experimental results validate the proposed method in different ADCs.

This paper presents a fully integrated 6.78 MHz active voltage doubler with a near-optimal on/off delay compensation scheme, achieving the maximized AC to DC power conversion efficiency (PCE) and voltage conversion ratio (VCR) for implantable medical devices (IMDs). In the proposed active voltage doubler design, we build sampling-based feedback loops for the real-time active diode on/off delay compensation. The proposed active voltage doubler was designed with a standard CMOS 0.35 Mm process. It achieves a peak PCE of 92.2% with a 500 Ω load, and a peak VCR of 1.92 with a 2 kfí load, improved by 10% and 33%, respectively, when compared with the voltage doubler without the delay compensation scheme. The input range of this design is from 1 V to 1.7 V with a load range from 200 Ω to 2 kΩ.

This paper presents a 10-bit 1-GS/s four-channel time-interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC). To suppress the time skew, the full rate master clock-based sampling technique is adopted. The effect of sampling switch mismatches on time skew is addressed. The measured time skew spurs caused by the sampling switch mismatches are around −52 to −55 dB at Nyquist input. Then, a tap-interpolating fractional delay filters-based digital background time skew calibration technique is proposed. Also, a full analysis of the effects of the various parameters on the time skew generated spur levels is presented, which indicates that the time skew error level is related to the length of calibration filters, calibration range, and bandwidth penalty. The subchannel ADC exploits a 250-MS/s SAR ADC with a low-cost high-speed subradix-2 searching technique. The reference interference of nonbinary TI ADCs is discussed and tolerated by the subradix-2 searching scheme. The proposed adders-based encoding circuit is optimized with lower propagation delay to meet high-speed requirements. The prototype was fabricated in a 65-nm CMOS technology. The measurement results show that the ADC achieves a signal-to-noise-plus-distortion ratio of 49.6 dB with a power of 15.95 mW and a figure of merit of 63 fJ/conversion step when operating at 1-GS/s and 458.1-MHz Nyquist input. The ADC core achieves an area of 0.158 mm2.

This paper presents an incremental A/D converter with a two-phase linear-exponential accumulation loop. In the linear phase, the loop works as a first-order structure. The noise coupling path is then enabled in the exponential phase thus boosting the SQNR exponentially with a few number of clock cycles. The uniform-exponential weight function allows data weighted averaging (DWA) to work well suppressing the DAC mismatch error. Fabricated in 65nm CMOS under 1.2V supply, the ADC achieves an SNDR/DR of 100.8dB/101.8dB with 20kHzBW, 550μW & 0.134mm 2 , resulting in FoMw and FoMs of 153fJ/176.4dB (SNDR), respectively.

This brief presents a time-interleaved (TI) successive-approximation-register (SAR) analog-to-digital converter (ADC) with an improved variance-based time-skew estimation technique, where we introduce a window detector (WD) based on a SAR ADC. It brings low hardware overhead and 10(4) times faster convergence speed when compared to the prior variance-based time-skew calibration. Postlayout simulation results of a 10-bit, 2-GS/s TI-ADC in 28-nm CMOS process verify the effectiveness of the proposed calibration. The results indicate that the signal noise and distortion ratio/spurious free dynamic range of the ADC improved from 41.9/48.6 to 53.2/63.3 dB after calibration. The total area and power are 0.105 mm(2) and 14.9 mW, respectively, where the WD occupies 0.0015 mm(2) and 0.55 mW.

This paper discusses design methodologies for highspeed SAR ADCs. A comparison of various architectures and the study of benefits and limits identify the best solution for highspeed and medium resolution. It is an interleaving architecture with the channel implemented by a fast coarse SAR quantizer and 2-way time-interleaved (TI) fine SAR ADCs. We propose a floatthen-write code transfer technique for optimizing the transfer sequence and reducing the reference interference. Furthermore, we also study and compare the output impedance of the reference generation as well as the reference interference for the optimized code transfer scheme and the conventional bit-by-bit in both single-channel and TI scenarios. In addition, the mismatches in TI channels and two sub-ADCs are discussed. A 10-bit test vehicle fabricated in 65-nm CMOS confirms experimentally the proposed methods operating with 1.2-V supply at 700 MS/s. The circuit occupies an active area of 0.084 mm(2) and achieves a signalto-noise and distortion ratio at a Nyquist of 53.3 dB, with a power consumption of 9.5 mW. The Walden figure-of-merit is 36 fJ/conversion-step.

This paper presents a 2x time-interleaved 7-b 2.4-GS/s 1-then-2 bicycle SAR ADC in 28-nm CMOS. The process-voltage-temperature sensitivity of a multi-bit SAR architecture has been improved by the proposed 1-then-2 bicycle scheme with background offset calibration. With the pre-charge reduction scheme, the traditional large switching energy and time consuming pre-charge operation have been removed, which simultaneously enables a simple control logic without the need of a V-cm voltage. Besides, a background offset calibration is implemented on chip which does not involve any extra phase or calibration input signal. Its operation is well embedded within the 1-then-2 bicycle architecture, thus leading to a very minimal modification of the ADC core. With an improved fringing DAC structure and a high-speed dynamic logic circuit, a single-channel ADC can work at 1.2 GS/s under a 0.9-V supply. Using two-way time interleaving, the prototype samples at 2.4 GHz and consumes 5-mW power including the on-chip background offset calibration. It exhibits a 40.05-dB SNDR at Nyquist, leading to a Walden FoM of 25.3 fJ/conversion step. Measurement results show that the SNDR of the ADC can be kept above 38 dB at 2 GS/s under a wide range of temperature, supply, and input common-mode variation.