Direct time-of-flight light detection and ranging is widely used for real-time, long-range three-dimensional sensing. It requires narrow optical pulses with high peak power to achieve high detection resolution and long range, imposing high demands on the laser diode driver (LDD) in the LiDAR transmitter. Monolithic GaN integration is well-suited for LDD design, as it minimizes gate-drive loop parasitics and offers devices with superior figures of merit. However, conventional GaN-based gate drivers suffer from limited driving capability due to the lack of suitable p-type devices. This article presents an FET-controlled LDD based on a 0.25-mu m GaN-on-Silicon process. A 3x self-circulating charge pump and zero-voltage-drop fast-charging switches strengthen the predriver, enabling high-speed switching of the GaN control switch. Experimental results show that the proposed LDD achieves a 10 A peak driving current with fast edge transitions of 434 ps (rise) and 252 ps (fall). Dead time insertion and an on-chip filtering capacitor suppress shoot-through current in the final stage of the predriver. The LDD exhibits an average power loss of 420 mW at 10 MHz and achieves a peak efficiency of 92.44% .

This article presents a synergetic power-delivery architecture (SyPoDA) that enables simultaneous 3-cell Li-ion flash charging and single-inductor dual-output (SIDO) point-of-load (PoL) regulation from a USB-PD 3.2 bus. Instead of using separate charger and PoL converters, SyPoDA merges an interleaved 2:1 switched-capacitor (SC) flash charger with a proposed hybrid SIDO converter, so that the high-voltage (HV) power stage and flying capacitors are shared by the charging and load-supply paths. The proposed hybrid SIDO topology achieves voltage-conversion-ratio-independent inductor current reduction and uninterrupted output-current delivery, thereby reducing the inductor volume and output decoupling capacitance without switch-current gathering. To support compact HV integration, fully integrated pulsed-current gate drivers (PCGDs) are developed to reduce the required on-chip bootstrap capacitance while preventing gate-voltage degradation. Fabricated in a 180-nm BCD process, the prototype occupies a 117-mm3 3-D volume and converts a 15-to-28-V input to concurrent 12.6-V, 3.3-V, and 1-V outputs. It achieves 92.1% peak efficiency at 42 W and supports 80-W maximum output power.

This article presents a scalable hybrid DC-DC converter module for compact CPU/GPU power delivery. The proposed complementary dual-mode reconfigurable topology combines two extended dual-path switched-capacitor cells through a DEMUX path, enabling a continuous 0.4–1.5-V output from a 1.8-V input while maintaining full-range inductor-current reduction. The overlapping voltage-conversion-ratio (VCR) regions avoid extremely narrow duty ratios near the mode boundary and support smooth hot switching, with a current capability enhancement factor ( $I_{\mathrm {LOAD}}$ / $I_{\mathrm {L,DC}}$ ) of 1.33–2 over the targeted range. An N-phase interleaving scheme further exploits the phase in which the flying capacitor is paralleled with the output capacitor, thereby enhancing the globally equivalent output capacitance and reducing both output ripple and flying-capacitor hard-charging stress. A fully integrated gate-driver scheme with a shared charge pump and bootstrap capacitor reduces off-chip components, while a $V^{2}I_{\mathrm {L}}$ adaptive-on-time controller improves transient recovery. Fabricated in a 180-nm CMOS process, the prototype integrates the power stage, drivers, and controller in 4.86 mm2. A single module achieves 96.7% peak efficiency and 2.5 A maximum load, and a four-module interleaved prototype delivers 10 A with 96% peak efficiency using a 94.7%-reduced global output capacitor.

This letter presents a dummy-free and low-power LDO designed for long-term standby applications. The proposed LDO eliminates the conventional dummy current by using an error amplifier-based biasing scheme, significantly reducing standby power consumption. To further enhance transient response under low quiescent current (IQS) conditions, a modified buffer adaptively adjusts its bias current, and a slew-rate enhancer operates without any static current. The LDO exhibits less than 70 mV undershoot for 0-to-140 mA load steps with sub-1-μA IQS.

This paper presents a voltage-mode buck converter employing an oversampled multi-phase-ramp (OSMR) PWM control technique to achieve enhanced load transient response. The proposed OSMR-PWM scheme utilizes N-phase time-interleaved ramp signals to sample level crossings with the error amplifier output, enabling rapid detection of output voltage (VOUT) transients. Unlike transient enhancement techniques, such as ripple-based control and other nonlinear methods that increase the duty cycle, the proposed technique does not alter the compensation logic of constant-frequency PWM control. It solely increases the sampling frequency, thereby mitigating the phase margin degradation caused by the zero-order hold (ZOH) effect inherent in the sampling process. Consequently, the proposed approach achieves a faster response to any load transient without introducing VOUT overshoot. In contrast to conventional voltage-mode PWM control, this approach improves transient performance by effectively boosting the loop bandwidth, without increasing the power stage switching frequency (FSW). Implemented in a 180-nm BCD process, the proposed converter was simulated as a 12:1 step-down converter operating at 1MHz FSW. The results demonstrate a 61.1% reduction in VOUT droop (from 103.2mV to 40.1mV) under a 1A/ns load step while completely eliminating overshoots. Furthermore, it achieves an average 35% reduction in voltage droop under transient load steps applied at different points within a single switching cycle. Additionally, this work achieves a peak efficiency of 96.13% for a 12V-to-1.2V conversion.

This letter presents a reconfigurable dual-path switched-capacitor hybrid buck converter with a wide input-voltage range for USB-powered point-of-load applications, featuring multiple optimal efficiency points (MOEP) and inductor current I-L,I-DC reduction. MOEP is achieved by dynamically reconfiguring the switching phases across different voltage conversion regions. This approach minimizes conduction losses in both the power inductor and high-voltage switches, allowing for the use of more compact power components. Using a small inductor (6.7 x 6.5 x 6.1 mm(3), direct current resistance (DCR) = 46.9 m Omega) and a flying capacitor (6.14 mm(3)), the converter prototype supplies a 5-V output with peak efficiency of 98.94%, 96.48%, and 91.95% for 9, 15, and 48 V input, respectively. The measured peak power density reaches 2245.86 W/in(3) at a 10-A load.

This article presents a power- and area-efficient switched-capacitor (SC) ac-dc converter in low-voltage (LV) CMOS for mains-powered Internet of Things (IoT) applications. The proposed converter adopts a single-stage series-capacitor architecture with fine-grained pre-rectification regulation, eliminating the need for intermediate high-voltage (HV) dc capacitors or HV dc-dc stages, thereby reducing form factor and device cost. By introducing dynamic reallocation of flying capacitors (C-FLY) and output capacitors (C-OUT), together with active source-detaching operations, the design achieves optimized capacitance utilization, extended rectifier conduction duty, and suppressed output ripple, resulting in enhanced efficiency and improved power density. Furthermore, the proposed scheme enables the use of 5-V CMOS devices throughout the converter, substantially lowering conversion losses and process cost. A detailed circuit model is developed to optimize capacitance assignment within the proposed SC ac-dc architecture. Fabricated in a 180-nm bipolar-CMOS-DMOS (BCD) process with an active area of 1.71 mm(2), the prototype achieves a peak efficiency of 90% and sustains 85.6% efficiency at a maximum output power of 9.11mW. It demonstrates a maximum system power density of 858 mW/mm(3), supporting compact integration with small-form-factor IoT devices. The converter accommodates 85- 230 V-RMS universal ac mains and regulates a 2.6- 5 V-DC output for load currents up to 2.4 mA.

IEEE Young Professionals in Circuits and Systems YPCAS organized a successful professional development event on Tuesday 24 June 2025 at the historic former Faculty of Medicine, University of Paris, France, as part of the IEEE Interregional NEWCAS Conference NEWCAS 2025. Under the theme Sustainability and EcoDesign in Electronics, the event brought together experts, researchers, and students to explore sustainable microelectronics design, circular electronics, life-cycle assessment, and eco-innovation, attracting significant participation and fostering exchanges between established professionals and early-career researchers.

This article presents a multi-phase multi-path hybrid switched-capacitor (SC) buck converter for 9-48 V-input point-of-load applications. The proposed topology uses interleaved SC cells operating at a higher frequency than the high-voltage stage, resulting in phase-balanced capacitor charge/discharge, thereby mitigating the effects of SC current gathering. In addition, the multi-phase operation decouples the high-voltage-stress power cells from high-current-conduction paths, reducing the inductor current under high-step-down conversions. Fabricated in a 180-nm SOI process with 5.7mm(2), the proposed converter achieves a measured peak efficiency of 88.3% and a current density of 176 A/cm(3) over an input range of 9-48 V and an output of 0.8-1.2 V, using only 11.35 mm(3) in passive volume.

This letter presents a reconfigurable dual-path (DP) switched-capacitor (SC) hybrid buck converter with a wide input-voltage range for USB-powered point-of-load applications, featuring multiple optimal efficiency points (MOEP) and inductor current IL,DC reduction. MOEP is achieved by dynamically reconfiguring the switching phases across different voltage conversion regions. This approach minimizes conduction losses in both the power inductor and high-voltage switches, allowing for the use of more compact power components. Using a small inductor (6.7×6.5×6.1 mm3, DCR = 46.9mΩ) and a flying capacitor (6.14mm3), the converter prototype supplies a 5V output with peak efficiency of 98.94%, 96.48%, and 91.95% for 9V, 15V, and 48V input, respectively. The measured peak power density reaches 2245.86 W/in3 at a 10A load.

This article presents a reconfigurable switched-capacitor (SC) DC-DC converter that achieves improved overall efficiency over a fine-grained conversion-ratio range, applicable to on-chip surround power delivery (SPD) in compact and lightweight devices. We propose a nesting-connected reconfigurable SC topology generation method, attaining fine-grained subdivision of reconfigurable voltage conversion ratios (VCRs) using a limited number of flying capacitors (C-FLYs). We also propose a normalized modeling method to evaluate the steady-state conduction-loss property for the nesting-connected arithmetic progression (NAP) topology implemented in this work. Modeling results demonstrate that the NAP topology enables fine-grained VCR generation and improved fast-switching-limited conduction loss characteristics, compared with the conventional series-connection method. In addition, due to its inherent property of multiple output charge-delivery paths, the proposed NAP converter is suitable for on-chip SPD to achieve a more uniform conduction charge distribution. Fabricated in a 180-nm CMOS process using standard 5-V devices, the proposed SC converter occupies an active area of 3.432 mm(2). It utilizes eight C-FLYs in 01005 packages, totaling a volume of only 0.128 mm(3), to achieve 25 inherent step-down VCRs of this NAP topology, ranging from 0.11 to 0.67. Thus, the converter can convert a 5-V input to a wide-range output of 0.35-3.3 V. Measurement results demonstrate a peak efficiency of 92.34% at 50-mA output current and a maximum capable load current of 500 mA.

This paper presents a self-powered isolated gate driver module that employs a vertical power-drive loop and resonant tracking scheme to achieve both high power density and high efficiency. The module integrates a high efficiency LLC driver, a low-profile transformer (XFMR), and an isolated gate driver within a vertical stacked structure, significantly reducing the footprint and parasitic interconnects. A resonant tracking scheme adjusts the fSW to minimize the coil current and loss. The low-profile XFMR uses flexible-printed-circuit-based (FPC) coil and achieves thickness of 2.0mm. The proposed module delivers a peak efficiency of 81.2% while achieving a power density of 36.5mW/mm³ with a 6.3W maximum output power, making it suitable for compact isolated power delivery in industrial and automotive applications.

The rapid advancement of AI-powered wearable devices, such as augmented reality glasses, has driven the emergence of customized low-power multimodal-processing SoCs and integrated power delivery system with stringent physical constraints, as shown in the Fig. 1 (left). Conventional centralized power delivery schemes using inductor-based topologies suffer from problems of localized hot spots and voltage drops due to the extended power delivery network (PDN) routing. Therefore, this work proposes a surrounding power delivery (SPD) architecture utilizing a stretchable arithmetic progression (SAP) switched-capacitor (SC) DC-DC and further integrates heat distribution considerations together with electrical performance optimizations. As a high power density (PD) solution, SC-based converters are particularly advantageous as advanced ring power supply scheme [1] or our proposed SPD architectures. However, the reconfigurable SC (RSC) converter often faces high implementation costs due to exponential-increased number of switches required as voltage conversion ratio (VCR) levels become finer-grained. While a series-connected RSC scheme can extend and subdivide the inherent VCR range without adding extra power switches, it introduces suboptimal conduction losses in each phase, resulting in reduced efficiency across the entire VCR range. By stretching the output paths, the reconfigurable SAP SC converter supports a stepdown from 5 V input voltage ($V_{\text {IN }}$) to a programmable output range of $0.35-3.3 \mathrm{~V}$ with 25 effective VCRs from $3: 2$ to $9: 1$ by only 8 flying capacitors ($C_{\text {FLY }}$), offering a highly efficient solution for power delivery in compact, energy-constrained systems. By distributing the power delivery network around the load circuit, it reduces the formation of hot spots and alleviates the IR voltage drop issues. Realizing an ultra-thin and lightweight implementation with a total thickness of approximately 1.5 mm, the proposed SAP SC converter achieves a peak efficiency of 92.3% and a maximum output power of 650 mW, validating the suitability of the proposed SPD scheme for compact, power-efficient applications. Mitigating the power conversion efficiency (PCE) degradation in series-connected RSC converters, it operates with high efficiency ($\geq 75 \% $) across a wide output voltage (Vout) range (0.44 V to 3.15 V).

Recently, dual-path (DP)-based switched-capacitor (SC) hybrid converter topologies have become favorable when addressing the requirement of wide-range power supplies with high efficiency and high power density in highly-integrated intelligent systems [1]–[7]. In addition to meeting the above characteristics, the power supply noise level is also critical to the overall performance in a multi-module system. The DP-based structures, using the SC paths to achieve input/output charge transfer, inevitably cause hard-charging noise and losses, especially under high-step-down voltage conversion ratios (VCRs) (extreme duty ratio). Furthermore, under higher input voltage, the efficiency and switching noise of most PWM converters are seriously affected by the commonly existing hard-switching effect. Although these issues can be alleviated by increasing the number of SC stages or adding interleaved branches, this increases the system complexity and compromises the reliability.

This work presents an efficient switched-capacitor (SC) AC-DC converter for IoT systems powered by mains in $120 V_{\text{RMS}}/230 V_{\text{RMS}}$ standards. To eliminate using high-voltage (HV) silicon devices to preserve conversion efficiency and reduce cost, we propose a series-capacitor single-stage AC-DC structure with a fine-grained SC pre-regulation network and active source detaching function, which achieves rectifier conduction loss reduction, output conduction duty extension, and output ripple reduction. At the same, the pre-regulation flying capacitors $(C_{\mathrm{F}})$ can be reallocated to be in parallel to $C_{\text{OUT}}$ dynamically according to load conditions, further improving the output ripple and enhancing total capacitance utilization. Fabricated in a 180-nm process using all 5-V CMOS transistors, the converter supplies an output $(V_{\text{OUT}})$ of 2.6~5V from an $85\sim 230V_{\text{RMS}}$ input $(V_{\text{IN}})$. It outputs a maximum power of 9.11mW with 85.6% efficiency and $858\text{mW}/\text{cm}^{3}$ overall system power density.

This paper presents a single-mode three-phase dual-path hybrid buck-boost (DPHBB) converter, featuring enhanced inductor DC current (I-L,I-DC) reduction and flying-capacitor (C-F) inrush current suppression over a wide voltage conversion ratio (VCR) range for lithium-ion battery-powered devices. The proposed converter eliminates topology-level mode transitions thanks to the multiple voltage options of V-IN, 2V(IN), and GND for the inductor switching operations. With an input of 2.7 similar to 4.2V, the proposed DPHBB converter provides three selectable output levels of 3.4V, 1.8V, and 1V. Incorporating an auxiliary C-F2 path to the output in parallel with the inductor branch, the inductor current (I-L) can always be lower than the load current (I-LOAD) across the entire VCR range, reducing the total conduction loss. Moreover, the three-phase operation prevents excessively short conduction duration for the C-F, effectively suppressing the C-F inrush current in narrow-duty hard-charging conduction cases. Implemented in a 180-nm BCD process, the proposed converter achieves 97.47% peak efficiency when converting a 2.7-V input to a 3.4-V output at an ILOAD of 0.3A using an inductor with 110-mO DC resistance (DCR).

This paper presents a single-channel bidirectional capacitive digital isolator featuring a dynamic time-slot allocation architecture with forward-path-prioritized transmission for ultra-low-latency operation. It combines a multiple-pulse-coding scheme for robust reverse-channel communication. Implemented in a 0.18-μm BCD process, this work demonstrates 5.7ns forward-path propagation delay at 100 Mbps data rate and 70ns reverse-path delay at 10 Mbps, achieving simultaneous bidirectional operation. Simulation results confirm a common-mode transient immunity (CMTI) of 500 kV/μs, representing a significant improvement over the conventional isolation solutions.

Battery-powered portable electronics typically require a battery charger, a battery-to-PoL converter, and a direct PoL converter with high efficiency and power density to accelerate charging, mitigate thermal issues, enhance portability, and prolong battery life. However, as shown in Fig. 1, the battery charging power ($P_{\mathrm{CHG}}$) is severely impacted by the USB cable loss ($P_{\text {Cable }}$) due to the high cable current ($/_{\text {cable }}$) at elevated charging levels with limited input voltage ($V_{\text {In }}$). In addition, when the power cable is connected, directly supplying the load from the cable input can accelerate charging and reduce battery wear. Further, an efficient battery-to-PoL converter prolongs the battery life after the plug is removed. Prior-art charger designs in [1] and [2] utilize the USB cable as the inductor to improve power density. Nevertheless, the device-end cable terminal acts as a switching node, preventing simultaneous parallel PoL supply and battery charging. The AVS function in the latest USB PD standard enables the switched-capacitor (SC) converter to be a favorable choice for battery charging as $V_{\text {IN }}$ can be adjusted with a fine step of 100 mV by the source-end. For PoL converters, prior SC hybrid topologies offer high power density by reducing $V_{\text {sw }}$ [3], [4] or $I_{\text {L,dc }}$ [5], [6], [7]. Still, these designs are constrained by inherent trade-offs among $/_{\mathrm{L}, \mathrm{Dc}}$ reduction, $C_{\mathrm{F}}$ inrush current ($/_{\mathrm{CF}}$), voltage conversion ratio (VCR) range, and hard-charging loss. Simultaneous charging and supply (CaS) schemes that combine an SC charger and PoL converters are attractive to improve the efficiency and power density from a power delivery architecture perspective [8], [9]. However, [8] suffers from a large $I_{\mathrm{L}, \mathrm{DC}}$, and [9] still faces the hard-charging loss between $C_{F}$ and $C_{\mathrm{o}}$. In addition, both cannot support a wide $V_{\text {In }}$ range, e.g., over 28 V due to the limited VCR in the 2:1 SC stage. To address these concerns, we propose a CaS converter that achieves simultaneous $1 \mathrm{~S} / 2 \mathrm{~S}$ battery charging and soft-charging operations in the PoL end with reduced $I_{L, \text { DC }}$ in a wide $V_{\text {IN }}$ range.

In this letter, an E-Mode GaN-Si(100) monolithic heterogeneous integration cascode switch (RBMHIC-switch) with reverse blocking compatibility on a SiC substrate with an AlN buffer layer is demonstrated. The RBMHIC-switch with L-GD of 22 mu m showed a threshold voltage (V-TH) of 2.64 V, a large forward gate voltage swing of 16.27 V, a turn-on voltage (V-ON) of 0.3 V, and an extremely low reverse leakage current (IR) of 3.5x 10(-4) mA/mm at -2000 V. The forward breakdown voltage (V-FBR) of 2264 V and reverse breakdown voltage (VRBR) of 2183 V with a specific on-resistance (R-ON,R- SP) of 3.74 m Omega center dot cm(2) were achieved, resulting in a forward power figure of merit (PFOM = V (2)(BR) /R-ON,R-SP) of 1.35 GW/cm(2) and reverse PFOM of 1.27 GW/cm(2). The ratio between dynamic-R-ON and static-R-ON was 1.104 and 1.127 after a 10 ms 1900 V drain stress voltage (VDS-OFF) and a 10 ms -1900 V VDS-OFF (delay time = 1 mu ) for the RBMHIC-switches, respectively, which were the best among all existing GaN power devices with reverse blocking capability. The thermal resistance at different temperatures was also extracted. The RBMHIC-switche shows decent overall characteristics as compared to the reported results.

For applications requiring both low-noise and high-efficiency such as sensors, data converters, and RF [1], we propose a combined inductor-boost / LDO step-up converter scheme employing output-referenced feedback control. The boost stage is operated with high voltage-conversion-ratio (VCR) to maximize efficiency while a quiet rail is provided at the output of the LDO for high supply-noise rejection. Choice of LDO drop-out voltage (VDROP) is a compromise of switch noise rejection vs. power loss. At high VCR, dynamic loss can be reduced by increasing the inductor peak current while reducing the switching frequency but at the expense of larger VBST ripple noise. Thus, for applications that require a high-voltage and low-noise supply, an optimized VDROP range can be found with respect to efficiency, as shown in the bottom right corner of Floura 1. For applications needing >20V supply, the optimized $\mathrm{v}_{\text{DROP}}^{\circ}$ region (≈0.5V) is also sufficient for circuits to operate. Therefore, in this work, the outout of the Boost stage (VBST) and the output of the LDO stage $(\mathrm{V}_{OUT}$ serve as a local supply rail and ground rail, respectively, as shown in Figure 1. The control circuits for these cascaded blocks, including the bandgap (BGR), loop-regulation circuitry, and the top-switch-control-logic are all realized between the two rails (i.e “output-referenced”) with local effective supply voltage equal to $\rightarrow\leftrightarrow\cdot \mathrm{r} VDROP$ As a result, the shunt current consumed between the two rails is re-used by the output load. When the load current $l_{LOAD}$ is higher than the current consumed by the circuitry in the VDROP rail domain, the current efficiency of the LDO stage approaches 100%. Figure 1 includes an efficiency comparison between a conventional boost architecture and the proposed method; for high VCR and light load conditions, the current reuse scheme offers notable improvement (up to ≈85% vs. ≈75%). The proposed Shunt-Current-Reuse structure is therefore an optimum choice for LiDAR-like applications that operate under high supply voltage (> 20V) and with a prolonged light load $(< 10\text{mA})$ condition [2].