Memristive technology mitigates the memory wall issue in von Neumann architectures by enabling in-memory data processing. Unlike traditional complementary metal-oxide semiconductor (CMOS) technology, memristors provide a new paradigm for implementing cryptographic functions and security considerations. While prior research explores memristors for cryptographic functions and side-channel attack vulnerabilities, our study uniquely addresses memristor-oriented countermeasures. We review different memristive crossbar configurations, implement a four-bit S-box cryptographic function, and analyse memristor-oriented hiding and masking techniques using a self-rectifying passive crossbar. Our findings confirm the efficacy of memristor-oriented hiding techniques but highlight limitations in memristor-oriented masked dual-rail pre-charge logic (MDPL) masking methods. Effective MDPL masking depends on specific power consumption conditions, i.e. the power profile of input data ‘01’ and ‘10’ are not clearly distinguishable from ‘00’ and ‘11’, which, however, are not satisfied across various memristive logic families. Despite passing t -tests, xor4Sbox with CRS-based MDPL masking failed stochastic approaches owing to power consumption differences. Our study prioritizes memristor-oriented countermeasures, advancing the understanding of challenges and opportunities in memristive technology for cryptographic functions. This article is part of the theme issue ‘Emerging technologies for future secure computing platforms’.

Memristors, as emerging nano-devices, offer promising performance and exhibit rich electrical dynamic behavior. Having already found success in applications such as neuromorphic and in-memory computing, researchers are now exploring their potential for cryptographic implementations. In this study, we present a novel power-balanced hiding strategy utilizing memristor groups to conceal power consumption in cryptographic logic circuits. Our approach ensures consistent power costs of all 16 logic gates in Complementary-Resistive-Switching-with-Reading (CRS-R) logic family during writing and reading cycles regardless of Logic Input Variable (LIV) values. By constructing hiding groups, we enable an effective power balance in each gate hiding group. Furthermore, experimental validation of our strategy includes the implementation of a cryptographic construction, xor4SBox, using NOR gates. The circuit construction without the hiding strategy and with the hiding strategy undergo T-test analysis, confirming the significant improvement achieved with our approach. Our work presents a substantial advancement in power-balanced hiding methods, offering enhanced security and efficiency in logic circuits.

AbstractSelf-rectifying memristive devices have emerged as promising contenders for low-power in-memory computing, presenting numerous advantages. However, characterizing the functional behavior of passive crossbar arrays incorporating these devices remains challenging due to sophisticated parasitic currents stemming from rich memristive dynamic behavior. Conventional methods using read margin assessments to evaluate functional behavior in passive crossbars are hindered by the voltage divider effect from the pull-up resistor. In this study, we propose a novel performance metric, $$\Delta$$ Δ SC, harnessing sneak path currents to assess functional behavior. Through the application of a pair of negative rectification factors, $$\text {RF}_\text {n, L}$$ RF n, L and $$\text {RF}_\text {n, H}$$ RF n, H , we comprehensively delineate dynamic rectification behavior in both positive and negative bias regimes, as well as in low-resistance state and high-resistance state, deviating from conventional metrics such as on/off ratios, nonlinearity, and rectifying factors. Notably, $$\Delta$$ Δ SC provides a quantitative evaluation of the interaction between sneak path currents and read margin, demonstrating its efficacy and addressing a pivotal research gap in the field. For instance, employing self-rectifying BiFeO$$_3$$ 3 memristive cells featuring $$\text {RF}_\text {n, L}$$ RF n, L = 1.22E3 and $$\text {RF}_\text {n, H}$$ RF n, H = 9.27, we showcase the successful functional performance of a passive crossbar array, achieving $$\Delta$$ Δ SC < 2.19E−2, while ensuring a read margin > 0.

The discovery of memristors has presented a novel paradigm for performing computations within memory, effectively addressing the limitations inherent in von-Neumann architectures. Based on this breakthrough, the utilization of the multistate characteristics of memristive devices holds the potential to enhance data storage density and computational efficiency. BiFeO 3 (BFO)-based memristive devices have gained attention due to their analog switching behavior, high on-off ratio, good data retention, low energy consumption, and the absence of any forming process. In this work, the ternary negation, implication and a one Trit ternary adder is implemented in Łukasiewicz logic with BFO memristors leveraging the analog multilevel programming capabilities in both SET and RESET directions.

Self-rectifying analog memristors have emerged as promising components for neuromorphic computing systems due to their inherent rectifying behavior and analog resistance states. Among these devices, BiFeO3 (BFO) memristors have shown exceptional performance, attributed to the accumulation and migration of oxygen vacancy ( V-o()). However, the movement of V-o() within the structure of the device presents challenges in optimizing their performance. To address this, the insertion of an interfacial layer has been proposed as a strategy to change the movement of V-o() and enhance the behavior of memristor. In this study, we investigate the optimization of self-rectifying analog memristors by inserting an interfacial layer in BFO memristors. The more significant nonlinearity in high resistance state branch we observed in the current-voltage relationship leads to better rectifying behavior and a larger on/off ratio at room temperature, which indicates that the interfacial layer improves rectifying behavior. Moreover, we propose a model based on the modulation of the interfacial barrier to elucidate the impact of the interfacial layer on the BFO memristor. These findings provide insight into the design principles for optimizing self-rectifying analog memristors, with potential applications in neuromorphic computing.

This study explores the feasibility of precisely tuning the resistive switching behavior of Au/BiFeO3/Pt/Ti/SiO2/Si memristors through controlled modulation of laser energy density during pulsed laser deposition (PLD). By systematically reducing the laser energy density within the fabrication process, notable alterations in the properties of the BiFeO3 (BFO) thin film are observed. As the laser energy density decreases, the grain size in the BFO film and the thickness of the film decrease. Furthermore, we obtain the minute structural variations in response to the diverse laser energy densities employed during the deposition process. Energy-dispersive x-ray spectroscopy analysis is employed to investigate the distribution of Ti4+ ions within the BFO thin film. The reduction in the grain size and film thickness, along with the prominent nucleation of specifically oriented grains, and the diffusion of Ti4+ ions, lead to the BFO memristor fabricated with a lower laser energy density having more grain boundaries and a shortened conduction path (grain boundary) in the thickness direction. Consequently, the enhanced movement of oxygen vacancies facilitates their preferential accumulation along the grain boundaries within the BFO layer, resulting in an augmented on/off ratio, rectification factor, and set current in the devices. Overall, our findings explain the significant influence of laser energy density in PLD on the microstructure and electrical properties of BFO thin films. Particularly, the lower energy densities are employed to improve electrical characteristics. This research not only enhances our fundamental understanding but also provides valuable insights into optimizing BFO memristors for reliable, robust, and practical applications.

Physical Unclonable Functions (PUFs) have gained widespread attention for their secure key storage, authentication, and anti-counterfeiting applications. While traditional PUFs based on Complementary Metal-Oxide-Semiconductor (CMOS) have been extensively studied, the emergence of memristors offers new opportunities due to their inherent device variations and distinctive resistive switching behaviors. This study explores the construction of reliable PUFs using self-rectifying analog BiFeO 3 (BFO) memristors. We assess the raw bit error rate (rBER) of the BFO-based PUF under varying voltage challenges and classify the switching behavior into stochastic, transition, and deterministic regions. As the primary objective of this study, we identify the sources of stochastic behavior in the three distinct regions while investigating the physical switching mechanism in BFO cells. Additionally, we propose a key storage method based on memristor variability, including an error correction scheme to enhance the reliability of PUF. This research contributes to a comprehensive understanding of PUF reliability and the underlying sources of intrinsic stochastic behavior in memristive technology.

Memristive devices based on the Valence Change Mechanism (VCM) are promising devices for storage class memory, neuromorphic computing and logic-in-memory (LIM) applications. They are suited for such a wide range of applications, due to their possibility for extreme dense integration, low power consumption and multilevel capabilities. Through LIM concepts, Boolean logic operations can be performed directly in memory. In many of these concepts, the resistance state of the device is interpreted as the logical input and output of the logic function, which is why these concepts are called ‘stateful’ logic. Most of the proposed ideas, however, are defined based on only binary switching VCM devices and neglect their multi-level capabilities. Extending LIM concepts towards multinary logic, e.g. a ternary logic, would increase the data density inside the memory array and reduce the number of devices required to perform a certain operation. In this work, we discuss two possibilities of realizing a ternary logic based on the analog switching in the RESET or in the SET direction. For both directions we verify the logic functionality by showing the basic operations of implication, negation and false operation, which together form a functionally complete logic. Additionally, for both switching directions, we discuss a 41-Trit ( ≈ 64-Bit) addition. For all investigations the physics-based compact model JART VCM v1b is used, which has been verified on the RESET direction multilevel properties of the TaO x devices.

While memristive devices are highly attractive as memory cells, they are also capable of performing computations, paving the way to futuristic in-memory computing architecture. Several memristive logic families have been proposed, and approaches to map gate-level logic circuits to such memristive implementations have been introduced. In this paper, we focus on the CRS logic family that offers several advantages compared to the more often considered IMPLY and MAGIC families. A central feature of CRS is the ability of one physical memristive device to realize varying logic gates over several clock cycles. Our method computes a schedule, i.e., an assignment which logic gate of a given circuit is executed on which memristive device during which clock cycles. Using an optimal MaxSAT model, it can minimize the resulting schedule’s duration (depth), the cost of the used memristors, or the cost of additional cache register cells, while satisfying all dependencies needed for correct computation. In addition to results of the scheduling procedure itself, we report a physical experiment that demonstrates one of the schedules and discuss the energy benefits of the CRS family.

Quick progress in memristive technologies has led to their consideration for several potential applications, many of which are security-critical. New possibilities of memristors, including their unique combination of non-volatile storage and compute capabilities, make them particularly attractive to edge applications, which are physically exposed to their users and therefore to potential attackers. Therefore, practical deployment of memristive circuitry for, e.g., cryptographic (sub-)modules or on-chip neural network inference, is only feasible when their vulnerability to physical attacks is understood and addressed. We evaluate experimentally one relevant class of physical attacks, namely side-channel attacks, under varying external conditions, namely temperature and magnetic fields. Using a small cryptographic construction, we evaluate both white-box and black-box attack varieties, using respective cryptanalytic techniques. Our results show that, while non-nominal conditions can complicate attacks, the information leakage remains and the secrets are extractable with additional knowledge about the memristive devices. This suggests the need to consider possible external disturbances during security evaluation.

The high demand for performance and energy efficiency poses significant challenges for computing systems in recent years. The memristor-based crossbar array architecture is enthusiastically regarded as a potential competitor to traditional solutions due to its low power consumption and fast switching speed. Especially by leveraging self-rectifying memristive devices, passive crossbar arrays potentially enable high memory densities. Nonetheless, due to the lack of a switching control per cell, these passive, self-rectifying memristive crossbar arrays (srMCA) suffer from sneak path current issues that limit the range of accurate operation of the crossbar array. In this work, the sneak path current issues in the passive srMCAs based on self-rectifying bipolar and complementary switching memristive devices are comparatively analyzed. Under consideration of the worst-case scenario, three reading schemes are investigated: one wordline pull-up (OneWLPU), all wordline pull-up (AllWLPU), and floating (FL) reading schemes. As a conclusion, despite different switching dynamics, both types of self-rectifying memristive devices can efficiently suppress sneak path current in the srMCAs. In the FL reading scheme, the sneak path current flowing through the unselected reversely biased memristive cells in the srMCA can be considered as an accurate estimation for the practical sneak path current in the srMCA. By analyzing the sneak path current in the srMCAs with a size up to 64 × 64, it is demonstrated that the leakage current plays a crucial role for suppressing the sneak path current, and the sneak path current via an individual cell exhibits a continuous decrease while the accumulated total sneak path current in the unselected reverse biased region is increasing with expanding the crossbar size. The comparative study on the bipolar and complementary memristive devices based srMCAs under diverse reading schemes reveals the influence of the switching dynamics on the sneak path current effect in the srMCAs, and provides a beneficial reference and feasible solutions for the future optimization of the crossbar topology with the intention of mitigating sneak path effects.

The spiking neural network (SNN), closely inspired by the human brain, is one of the most powerful platforms to enable highly efficient, low cost, and robust neuromorphic computations in hardware using traditional or emerging electron devices within an integrated system. In the hardware implementation, the building of artificial spiking neurons is fundamental for constructing the whole system. However, with the slowing down of Moore's Law, the traditional complementary metal-oxide-semiconductor (CMOS) technology is gradually fading and is unable to meet the growing needs of neuromorphic computing. Besides, the existing artificial neuron circuits are complex owing to the limited bio-plausibility of CMOS devices. Memristors with volatile threshold switching (TS) behaviors and rich dynamics are promising candidates to emulate the biological spiking neurons beyond the CMOS technology and build high-efficient neuromorphic systems. Herein, the state-of-the-art about the fundamental knowledge of SNNs is reviewed. Moreover, we review the implementation of TS memristor-based neurons and their systems, and point out the challenges that should be further considered from devices to circuits in the system demonstrations. We hope that this review could provide clues and be helpful for the future development of neuromorphic computing with memristors.

Memristive technologies offer fascinating opportunities for unconventional computing architectures and emerging applications. While memristive devices have received substantial attention as sources of entropy for security applications, security vulnerabilities of memristive technologies for implementing cryptographic circuits have been largely neglected so far. In this article, we provide the first in-depth analysis of power side-channel analysis against memristive cryptographic implementations based on both: physical experiments and simulations. We show that power consumption models developed for CMOS are not fully adequate for memristive circuits. In particular, the memory effect makes even input-independent initialization cycles vulnerable to attacks that would be fundamentally impossible in CMOS technologies. We propose a memristive-oriented Power Estimation Model (mPEM) integrated into the Stochastic Approach (StA) framework and demonstrate its effectiveness against larger-scale circuits. Finally, we demonstrate that attack countermeasures that were effective for CMOS fail for fundamental reasons in the memristive case.

With the advent of the Internet of Things, nanoelectronic devices or memristors have been the subject of significant interest for use as new hardware security primitives. Among the several available memristors, BiFe[Formula: see text] (BFO)-based electroforming-free memristors have attracted considerable attention due to their excellent properties, such as long retention time, self-rectification, intrinsic stochasticity, and fast switching. They have been actively investigated for use in physical unclonable function (PUF) key storage modules, artificial synapses in neural networks, nonvolatile resistive switches, and reconfigurable logic applications. In this work, we present a physics-inspired 1D compact model of a BFO memristor to understand its implementation for such applications (mainly PUFs) and perform circuit simulations. The resistive switching based on electric field-driven vacancy migration and intrinsic stochastic behaviour of the BFO memristor are modelled using the cloud-in-a-cell scheme. The experimental current-voltage characteristics of the BFO memristor are successfully reproduced. The response of the BFO memristor to changes in electrical properties, environmental properties (such as temperature) and stress are analyzed and consistant with experimental results.

With the advent of the Internet of Things, nanoelectronic devices or memristors have been the subject of significant interest for use as new hardware security primitives. Among the several available memristors, BiFeO_3 (BFO)-based electroforming-free memristors have attracted considerable attention due to their excellent properties, such as long retention time, self-rectification, intrinsic stochasticity, and fast switching. They have been actively investigated for use in physical unclonable function (PUF) key storage modules, artificial synapses in neural networks, nonvolatile resistive switches, and reconfigurable logic applications. In this work, we present a physics-inspired 1D compact model of a BFO memristor to understand its implementation for such applications (mainly PUFs) and perform circuit simulations. The resistive switching based on electric field-driven vacancy migration and intrinsic stochastic behaviour of the BFO memristor are modelled using the cloud-in-a-cell scheme. The experimental current-voltage characteristics of the BFO memristor are successfully reproduced. The response of the BFO memristor to changes in electrical properties, environmental properties (such as temperature) and stress are analyzed and consistent with experimental results.

Abstract With the advent of the Internet of Things, nanoelectronic devices or memristors have been the subject of significant interest for use as new hardware security primitives. Among the several available memristors, BiFe $$\mathrm{O}_{3}$$ O 3 (BFO)-based electroforming-free memristors have attracted considerable attention due to their excellent properties, such as long retention time, self-rectification, intrinsic stochasticity, and fast switching. They have been actively investigated for use in physical unclonable function (PUF) key storage modules, artificial synapses in neural networks, nonvolatile resistive switches, and reconfigurable logic applications. In this work, we present a physics-inspired 1D compact model of a BFO memristor to understand its implementation for such applications (mainly PUFs) and perform circuit simulations. The resistive switching based on electric field-driven vacancy migration and intrinsic stochastic behaviour of the BFO memristor are modelled using the cloud-in-a-cell scheme. The experimental current–voltage characteristics of the BFO memristor are successfully reproduced. The response of the BFO memristor to changes in electrical properties, environmental properties (such as temperature) and stress are analyzed and consistant with experimental results.

In the era of Big Data and Internet of Things (IoT), information security has emerged as an essential system and application metric. The information exchange among the ubiquitously connected smart electronic devices requires functioning reliably in harsh environments, which highlights the need for securing the hardware root of trust. In this work, by leveraging the uniform nonlinear resistive switching of emerging electroforming-free analog memristive device based on $\mathbf {BiFeO}_3$ (BFO) thin film, the security-oriented hardware primitive (SoHP) system is developed and optimized with high-security level. The SoHP system utilizes the distinguishable power conversion efficiency generated at second and higher harmonics in low resistance state (memristor with diodelike behavior) and high resistance state (memristor with high resistive behavior) of memristive devices. By exploring the significant influence of writing bias and operational frequency in sourcing input voltage on the dynamic switching behavior of memristive device, the novel 2-memristor encoding scheme and 1-memristor decoding scheme are developed for SoHP system, which realizes a frequency enhancement of 4000 times in comparison to 1-memristor encoding scheme and 2-memristor decoding scheme. The encoded data bits that generated from physically implemented SoHP system pass diverse statistical test suites (i.e. ENT, BSI, and NIST SP-800.22 statistical test suites), which indicates the high randomness distribution of the encoded data and the high-security level of the proposed memristive encoding system.

Computation based on the von Neumann architecture suffers from the data transfer between computation unit and memory, i.e. the so-called von-Neumann bottleneck. Thus, new computing paradigms emerge leveraging in-memory computing (IMC). Stateful memristor aided logic (MAGIC), which has attracted great attention in recent years, enables the realization of a functionally complete set of Boolean logic functions within a memristive memory array. Whereas typically digital-switching memristive devices are exploited, in this work, we investigate the realization of MAGIC gates using analog-switching BiFeO 3 (BFO) devices. The simulation results reveal that the MAGIC NIMP gates, as proposed for a digital-switching memristive device, do not work correctly with the analog BFO devices. By studying the input drift and blocking effect while operating MAGIC NIMP gate, we propose two alternative MAGIC gates by exploiting analog memristors, i.e. a NOR gate and a -P gate.

Emerging brain-inspired neuromorphic computing paradigms require devices that can emulate the complete functionality of biological synapses upon different neuronal activities in order to process big data flows in an efficient and cognitive manner while being robust against any noisy input. The memristive device has been proposed as a promising candidate for emulating artificial synapses due to their complex multilevel and dynamical plastic behaviors. In this work, we exploit ultrastable analog BiFeO3 (BFO)-based memristive devices for experimentally demonstrating that BFO artificial synapses support various long-term plastic functions, i.e., spike timing-dependent plasticity (STDP), cycle number-dependent plasticity (CNDP), and spiking rate-dependent plasticity (SRDP). The study on the impact of electrical stimuli in terms of pulse width and amplitude on STDP behaviors shows that their learning windows possess a wide range of timescale configurability, which can be a function of applied waveform. Moreover, beyond SRDP, the systematical and comparative study on generalized frequency-dependent plasticity (FDP) is carried out, which reveals for the first time that the ratio modulation between pulse width and pulse interval time within one spike cycle can result in both synaptic potentiation and depression effect within the same firing frequency. The impact of intrinsic neuronal noise on the STDP function of a single BFO artificial synapse can be neglected because thermal noise is two orders of magnitude smaller than the writing voltage and because the cycle-to-cycle variation of the current–voltage characteristics of a single BFO artificial synapses is small. However, extrinsic voltage fluctuations, e.g., in neural networks, cause a noisy input into the artificial synapses of the neural network. Here, the impact of extrinsic neuronal noise on the STDP function of a single BFO artificial synapse is analyzed in order to understand the robustness of plastic behavior in memristive artificial synapses against extrinsic noisy input.