This paper reviews recent developments in design of antennas and impedance matching networks for RF Energy Harvesting (RF-EH) at UHF. The antenna design is considered in conjunction with the requirements that it places on the impedance matching network (IMN), in order to match the load which is an RF to DC converter. It is shown that there may be advantages in using an interface impedance between the antenna and the IMN that differs from the conventional 50 Ω impedance. Various options are considered for the design of an IMN driving a rectifier load. A novel adaptive IMN architecture is proposed that can match two different load impedances, depending on the received power level. This can optimize Power Conversion Efficiency (PCE) over a range of different input powers that may be encountered in RF EH.
Post-quantum cryptography is one of the popular research topics today. The implementation of the proposed algorithms is also extremely important. In this study, the NTRU cryptosystem, which is one of the post-quantum cryptography candidate algorithms, is designed and run on an open source RV32IMC processor. New instruction candidates have been developed and integrated into the functional unit of the processor with a functional profiling method. The results show that NTRU cryptosystem can be accelerated by 32.3% with this simple method.
Physically Unclonable Functions (PUFs) allow to generate bitstrings for applications such as device identification, authentication, or key management. For real-world deployment, the industry has stringent requirements on reliability. In addition, as it greatly impacts the security of the whole application chain, the randomness produced by the PUF cannot be compromised. These two requirements are captured by the notions of dynamic randomness—to be minimized in order to improve reliability— and static randomness—to be maximized to increase security.In this paper, we illustrate the whole methodology on a delay-PUF called the loop-PUF. To meet the above requirements on dynamic and static randomness, the PUF’s behavior should be modeled and validated; such activities are described in the international standard ISO/IEC 20897. Modeling consists in establishing a stochastic model of the PUF, to predict bit error rates due to dynamic noise, and entropies of the static noise. The model is then verified, its parameters estimated, based on measures in representative environmental conditions.
Cellular neural networks were used with success in the past decades and helped laying the foundations of neural net-work applications in image processing. In the last few years convolutional networks have appeared and helped in the solution of complex practical problems. Meanwhile programming templates of cellular neural networks were designed by analytical methods, gradient based optimization is applied popularly in convolutional networks. In this paper we will demonstrate how these methods can be exploited using cellular networks and how they can be used to implement classification and feature extraction tasks, both with standard and memristive cell dynamics.
As Internet of Things (IoT) devices are increasingly used in industry and become further integrated into our daily lives the security of such devices is of paramount concern. Ensuring that the large amount of information that these devices collect is protected and only accessible to authenticated users is a critical requirement of the industry. One potentially inexpensive way to improve device security utilises a Physically Unclonable Function (PUF) to generate a unique random response per device. This random response can be generated in such a way that it can be regenerated reliably and repeatably allowing the response to be considered a signature for each device. This signature could then be used for authentication or key generation purposes, improving trust in IoT devices. The advantage of a PUF based system is that the response does not need to be stored in nonvolatile memory as it is regenerated on demand, hardening the system against physical attacks. With SoC FPGAs being inexpensive and widely available there is potential for their use in both industrial and consumer applications as an additional layer of hardware security. In this paper we investigate and implement a Trusted Execution Environment (TEE) based around a PUF solely implemented in the FPGA fabric on a Xilinx Zynq-7000 SoC FPGA. The PUF response is used to seed a generic entropy maximisation function or Pseudorandom Number Generator (PRNG) with a system controller capable of encrypting data to be useful only to the device. This system interacts with a software platform running in the ARM TrustZone on the ARM Cortex core in the SoC, which handles requests between user programs and the FPGA. The proposed PUF-based security module can generate unique random keys able to pass all NIST tests and protects against physical attacks on buses and nonvolatile memories. These improvements are achieved at a cost of fewer than half the resources on the Zynq-7000 SoC FPGA.
Data converters are ubiquitous in mixed-signal systems, becoming the computational bottleneck in traditional data acquisition and emerging neuromorphic systems. Unfortunately, conventional Nyquist data converters trade off speed, power, and accuracy. Therefore, they are exhaustively customized for special purpose applications. Furthermore, intrinsic real-time and post-silicon variations dramatically degrade their performance along with the CMOS technology downscaling. Here, we review on our neuromorphic analog-to-digital (ADC) and digital-to-analog (DAC) converters that are trained using the online stochastic gradient descent algorithm to autonomously adapt to different design specifications, including multiple full-scale voltages, number of resolution bits, and sampling frequencies. We demonstrate the feasibility of our converters by simulations and preliminary experiments using memristive technologies. We show collective properties of our converters in application reconfiguration, logarithmic quantization, mismatches calibration, noise tolerance, and power optimization. The proposed data converters achieve a superior figure-of-merit (FoM) of 1 fJ/conv.
During the last years, Physically Unclonable Functions (PUFs) have become a very important research area in the field of hardware security due to their capability of generating volatile secret keys as well as providing a low-cost authentication. In this paper, an introduction to Physically Unclonable Functions is given, including their definition, properties and applications. Finally, as an example of how to design a PUF, the general structure of a ring oscillator PUF is presented.
If not properly initiated, even-stage ring oscillators may resonate in undesirable ways. When this occurs, their output frequency can be higher than expected and they can no longer be employed as VCOs in PLL designs. In this paper, we analyze this issue and then we propose a novel startup circuit that can be used in differential, even-stage ring oscillators. This design is produced using a 0.30 µm CMOS process. Measurements performed on test chips show that our circuit always prevents spurious oscillation modes from arising. On the contrary, if the proper startup is disabled, unwanted modes may occur, especially at low temperatures or with little bias current. Moreover, consisting of just two MOSFETs per oscillator stage, the proposed circuit is also very simple and efficient in terms of area and power dissipation.
Improving the efficiency of convolutional neural networks (CNN) often relies on integer-only algorithms. Using boolean activations can bring further inference speed gain, and can make easier the design of CNN-specific ASICs. A convolutional algorithm called BoolHash that we propose here can additionally increase the inference speed several times, and permits functionalities that usually require more complex processing. A CNN model with 16-bit input weights, 8-bit filter weights and 1-bit activations was used to compare the speed of BoolHash to that of a classic weight-adder convolutional algorithm.
In this paper we study a new class of hysteresis memristor CNN (HM-CNN). The model under investigations contains a simpler state equation with hysteresis operator in the feedback circuit and resonant tunnel diode in the output. The dynamics is studied in different regions depending on hysteresis nonlinearity. The proposed HM-CNN exhibits various complex phenomena in hysteresis region by exploiting its local activity and edge of chaos. Some applications of HM-CNN model in nanostructures are provided.
Classical neural networks have transfer functions in their structures. These functions are different in solving different tasks and in different types of neural networks. In this paper, the authors use the tools of indexed matrices and one of the operators to change the properties of neural networks.
This paper reports a novel beamforming method based on Continuous Time Sigma-Delta Modulators (CT SDM) with feedforward (FF) programmable coefficients implemented as spatial FIR filters. This new method realizes analog beamforming in baseband and allows accurate beamsteering by programming banks of resistors. We present the theoretical framework and a proof-of-concept implementation as a spatio-temporal 250MHz signal bandwidth CT SDM in 40nm CMOS for a 9-channels phased array. This paper shows that the proposed method can significantly lower the ADC SNR requirements in phased-array receivers operating in the presence of multiple interferers inside the signal frequency band. Our method can enable power-efficient hybrid multi-link beam-forming when combined with the standard digital beamforming approaches.
This paper investigates the beam squint of direct conversion phased array transmitters with quadrature modulation and digital beam-forming. Beam squint occurs due to frequency dependent beam forming and leads to signal deterioration. It is analyzed in terms of EVM and maximum bit-rate, using both analytical and numerical computation. Various results illustrate the dependencies of the error mechanism on key design parameters in mm-wave transmitters. It is shown that having 14 elements and 120° scanning angle limits the theoretical maximum bitrate by 84% We show that using partial symbol delay in baseband, the EVM can be improved up to -30dB for 10 elements and more, without any apparent disadvantages. Moreover the bitrate theoretical maximum is increased by 4 times.
In this paper, we perform FPGA modeling of an event-driven all-digital phase locked loop (ADPLL) with asynchronous control. We perform the comparison with a theoretical model through a transient response, phase plane representation, and the order parameter. The hardware simulations showed a very good agreement with the theoretical model, which can be used for studying more complex ADPLL networks.
A novel Delay Line based bidirectional readout IC is proposed for Potentiostatic measurement which allows time-domain analysis of sensor current and offers highly linear (R 2 =0.9998), low noise and low power implementation. The architecture is implemented in 0.18μm process and can operate for two distinct input range (IR) ±10nA/±10μA, while the Delay Line consumes 3.6μW/150.7μW power, respectively. Due to its digital intensive nature, the architecture supports a wide variation in supply voltage 0.6V-1.8V, while ensuring little deviation of sensitivity.
We discuss the design of an area-efficient CMOS analog core-cell implementing a PUF derived from a two-neurons Cellular Neural Network (CNN). The study is based on both theoretical modeling and numerical simulations, proposing circuit solutions in which the area consumption is strongly reduced by eliminating state capacitors and relying on distributed parasitic capacitances only.
This paper presents a new approach to describe the analog power-down synthesis problem by combining two state-of-the art constraint programs to a unified, homogeneous constraint optimization problem that, in contrast to the previous approach, allows trade-offs between the two design goals "matching" and "area". Furthermore, enhanced symmetry constraints are incorporated by the new method. Experimental results show the efficacy of the proposed method.
The paper proposes a tool for the numerical simulation of the behavior of coupled oscillators based on Kuramoto model. The approach is based on constructing electrical circuit model for which Kirchhoff equations coincide with Kuramoto equations of the oscillator ensemble. A procedure to generate Spice netlist for the circuit has been developed. The procedure is based on the initial description of the Kuramoto model in the form of Matlab data structures.
A pulse width-controlled CMOS pulser for a semiconductor laser diode (LD) and a time-gated time-resolved 8×4 single-photon avalanche diode array with a time-to-digital converter (TDC) were designed on a single integrated circuit and simulated by using a 150 nm technology. The pulse width of the driving current can be adjusted from 0.5 ns to 2.5 ns with a resolution of 100 ps. The start time of the time-gating can be adjusted over a dynamic range of 4.8 ns with a resolution of 100 ps and, furthermore, a 121 ps time-gating can be achieved. The returning photons are detected by the TDC with a resolution of 50 ps and stored to the 128 14-bit counters for merging to the distribution time-of-flight histogram. The average power consumption of the whole system was 377 mW at a repetition rate of 10 MHz.
