Semiconductor companies using advanced technologies with FinFETs often rely on the foundry-provided SPICE model for reliability prediction. However, SPICE model has limitations in terms of its valid range of the operating conditions like voltage, temperature, etc. TCAD (technology computer aided design) simulation is not only critical for understanding semiconductor reliability physics, it can also bridge the gap to predict the device level reliability beyond the valid range of SPICE model. It is therefore, critical to calibrate the TCAD so that it represents silicon data reasonably well. In this paper, the calibration methodologies used to match TCAD with silicon-based SPICE model have been discussed for a 16nm FinFET technology. Self-heating effects (SHE) in FinFETs can cause severe reliability degradation. A calibrated TCAD deck has been used in this paper to study the SHE in FinFET into the operating conditions beyond the valid range of SPICE model.
Device failure can lead to operation instability and application performance degradation. To avoid this, restricting operational parameters can optimize long-term device reliability; however, to fully maximize device performance and capability a comprehensive failure analysis study is required. In this work we observed the regions of operation failure concerning current, voltage, and temperature stress on integrated CMOS/ReRAM memory cells. Voltage and current stresses were reported to show sharp device failure due to changes in conduction and energy mismatch, while temperature stress affected long-term device performance. This analysis will allow a greater grasp of parameter usage for future ReRAM based memory.
Anomalous NBTI degradation characteristics have been observed for pMOS transistors which had experienced plasma processing induced charging damage. This is a critical topic for correct NBTI lifetime predictions from antenna transistor structures with PID for p-type MOS and FinFET transistors with various thicknesses of SiO 2 or high-K gate dielectrics. Examples from the literature also depict this NBTI anomaly. A qualitative charge trapping model is described for root cause analysis. A proposed methodology demonstrates the correction of NBTI data from antenna transistor structures with PID.
Deep Trench Isolation (DTI) is a common termination technique in optoelectronics to minimize cross-talk between single devices fabricated on the same chip. However, DTI can also affect the performance of optoelectronic devices. In this work we simulate and model the influence of minority carrier recombination at the DTI interface on the quantum efficiency, i.e. responsivity, of Si photodetectors. We demonstrate that DTI interface recombination is a non-linear effect with respect to the applied irradiance and causes a non-linear response of the photodetector, which must be avoided for certain applications. Furthermore, we show that sufficiently high positive or negative fixed oxide charges can improve device performance by reducing the DTI interface recombination. To maintain the benefit of electrical cross-talk minimization in combination with an almost linear responsivity we propose a structure terminated with lateral deep trench metal oxide semiconductor capacitors (DTMOSCAPs) to control the passivation of the DTI interface by an applied gate bias. By means of TCAD simulations, we show that such a device is superior to default DTI structures in terms of responsivity as well as linearity.
The electrical characteristics of a transistor can deviate from its nominal behavior due to process variations, aging mechanisms, etc. In order to ensure the reliability of a design, circuit level simulations capturing this altered transistor behaviors have become increasingly important. In this paper we study the use of surrogate models to map changes in key transistor’s figures of merit into compact model parameters in order to shorten the path from reliability measurements to simulations.
