Forward body biasing (FBB) is among the simplest and most effective techniques that can be leveraged to improve the performance of dynamic comparators, as previous works have demonstrated. However, none of these works puts emphasis on comparing different FBB schemes and their robustness against large differential input swings. This is especially important when considering circuits that operate at supply voltages above 0.5 V, where several approaches can be adopted for biasing the substrates without causing the body-source junctions to turn on. This paper compares three different techniques: the clocked FBB (CFBB) proposed in [1], an improvement of CFBB and a new hybrid approach that achieves the best performance in terms of delay. For the sake of brevity, the scope of our experiments has been limited to the Strong Arm latch. All simulations were carried out in a 55 nm CMOS technology at 1 V supply and 2.4 GHz clock frequency.
A time-based compensator represents an effective solution to overcome the limitations of the traditional voltage mode controllers, as it allows to reduce both the die area occupation and the quiescent power consumption without compromising the control loop performances. Buck converters driven by high switching frequencies suffer from relatively low efficiency in medium/light load conditions, given the large power losses associated to the switching activity. Usually, to overcome this limitation the converter is operated in pulse frequency modulation (PFM), which makes it necessary to design an additional control loop and adds a DC offset to the output voltage as well. This paper proposes a variable switching frequency time-based control, able to operate the converter both in continuous and discontinuous current mode to guarantee high efficiency for a wide load current range. In addition, seamless frequency transition are obtained with a dedicated on-time correction circuit, which keeps the average inductor current constant upon variations of the operating regime. The proposed method boosts the efficiency in medium-light load conditions, ensuring an overall efficiency above 85% over a wide load current range. The effectiveness of this technique is supported by theoretical analysis and simulation results.
Post-layout simulation results of a current mode switching mode power amplifier (CM-SMPA) in 22 nm FD-SOI CMOS for a fully digital RF transmitter with a peak output power of 23.51 dBm (224.4 mW) at 3.6 GHz are presented. The CM-SMPA is driven by a pulse-width (PW) and pulse-position (PP) modulated signal for amplitude and phase control. To increase the amplitude dynamic range, the conductance (G) of the switches is also modulated. For a 64-QAM signal with 112.5 MBd, an error vector magnitude (EVM) of −32.50dB with a maximum adjacent channel leakage ratio (ACLR) of −40.81 dB in the neighbor channel is achieved. The average total efficiency and drain efficiency are 24.93 % and 32.12 % respectively. The large signal bandwidth potential of this transmitter concept is shown by a simulation of a 450 MBd 64-QAM with a channel bandwidth of 675 MHz.
This paper presents the development and optimization of a front-end circuit and the design of a monolithic sensor demonstrator with a high spatial resolution (hexagonal pixels with 50 μ m pitch) and sub-10 picosecond timing capability for the detection of ionizing radiation. The system combines a monolithic sensor in a SiGe BiCMOS process with a front-end architecture based on a SiGe Heterojunction Bipolar Transistor (HBT). The design of the prototype has been optimized to achieve improved timing performance while maintaining low power consumption by analyzing the trade-off between sensor input capacitance and power consumption. The goal is to achieve a timing resolution below 10 ps, a significant improvement over the previous prototype, which demonstrated a time resolution of 20 ps. This prototype has been developed in the framework of the MONOLITH H2020 ERC project.
This paper presents a new successive approximation algorithm that can digitize the second-order difference of signal samples rather than each sample point individually or plain difference of sample points. This method is able to drastically reduce the number of comparisons required to convert a new signal sample to digital numbers, from a fixed N comparisons commonly used in a conventional successive-approximation-register (SAR) analog-to-digital converter (ADC), to a number in between 2 and N for almost all the signal samples in an N-bit ADC. This proposed algorithm is implemented in MATLAB and tested on electrocardiogram (ECG) signals in this work. The experimental results show that our algorithm can reduce the number of comparisons by 58.75% compared to the conventional SAR ADC, and by 17.78% or more compared to several other state-of-the-art methods. In addition, it is able to reduce the DAC updating time by the same percentages, leading to lower power consumption in both DAC and digital parts of SAR ADC.
In this paper, a transient response improved output capacitorless low dropout regulator is designed in standard 0.13 $\mu$m CMOS technology. A method based on adaptively sense network (ASN) to increase the slew rate and provide extra discharge loop is adopted, which suppresses the undershoot and overshoot of output voltage. Simulation results reveal that the output voltage undershoot and overshoot is 97.03 mV and 140.87 mV, when load current step from 10 $\mu$A to 30 mA with the edge time is 100 ns, respectively. And the output voltage recovery time is less than 0.35 $\mu$s, the fast settle time is also achieved. Besides, the linear regulation of load and supply voltage is 0.043 mV/mA and 1.467 mV/V.
Sample rate conversion is a fundamental operation performed in the digital front-end of software-defined radio and all-digital receivers. Within this context, polynomial-based filters, such as the Farrow structure and its variants, are a sound solution when arbitrary resampling is required. This paper presents a design methodology and the results of the implementation on a field-programmable gate array (FPGA) device for a highspeed transposed Farrow structure based on a novel parallel architecture. The implemented architecture supported an input sample rate of up to 2.184 GHz with moderate utilization of the FPGA resources. Furthermore, signal-to-noise ratio and spurious-free dynamic range values higher than 87 dB and 98 dB were reported over a wide range of sample rate conversion factors. Our results may suggest an improvement in the trade-off between flexibility, complexity and throughput compared with previous work in the field.
This work presents wide-band/wide range Variable Gain Amplifier (VGA) based on the Quantized-Analog (QA) processing. The VGA is formed by an array of sub-units that amplify different portions of the input signal. The gain variation is obtained by acting on the signal correlation among adjacent slices that are eventually recombined on an output load. The VGA has been characterized, by inserting the VGA inside an optical RF front-end which includes a TIA stage and output buffer. Designed and layouted in 28nm CMOS, the VGA shows a gain variation of about 22 dB obtained in one stage, and a -3dB bandwidth of 29 GHz. At maximum gain, the average equivalent input-referred current noise is equal to 10.3 pA/$\sqrt{Hz}$ while the Total Harmonic Distortion (THD) is below 2.3% for a maximum output swing of 500-mV peak-to-peak differential. The VGA consumes 64 mW while the complete front-end 124 mW from a 1.2V voltage supply.
Simultaneous wideband input matching and gain performance while maintaining low core area is one of the big challenges of mmW amplifier design. In this work, the stacked common base (stacked CB) configuration is proposed for the input stage of an amplifier to achieve a good compromise between gain, input matching and area. The stacked CB topology is compared with the cascode and simple CB configurations to prove its validity. Finally, two G-Band amplifiers are designed with different input stage topologies: cascode and stacked CB. Both show very small core areas (0.066 and 0.085 mm 2 respectively) while maintaining gains of 22.8 and 22.5 dB, NF of 9.4 and 9.9 dB and GBW product of 317 and 346 GHz respectively that are comparable to the SoA. The stacked CB version shows a wideband input bandwidth of 76 GHz $(S11 < -10$ dB), making it a suitable choice for area-efficient and broadband input stages.
Miniaturization of electrochemical sensing devices for point-of-care, wearable and implantable diagnostics relies on CMOS potentiostat readouts that offer rapid and accurate test results. Conventional CMOS potentiostats are based on traditional analog blocks such as op amps and comparators, with a performance penalty in terms of power consumption and dynamic range. Time-based readout architectures offer unique advantages to achieve ultra-low power and low voltage operation without sacrificing small area and resolution. In this paper, we present the design of a CMOS potentiostat circuit with a current-mode time-based SAR ADC readout. The simulated results suggest that the readout channel can achieve an estimated energy efficiency of 1.5 pJ/bit from a 1.8 V supply. The proposed architecture can be readily scaled and programmed for a wide range of input currents, which makes it suitable for multiplexed multi-analyte systems.
In this paper is presented a fast-transient mitigation technique which applies to a self-timed, dual-loop Asynchronous Digital LDO. The number of conducting transistors is controlled by an Asynchronous Finite State Machine (AFSM) employing a linear-search algorithm that is able to operate without a clock oscillator. It relies on a simple Request-Acknowledge (REQ-ACK) protocol to manage the power stage. The proposed mitigation technique has two components. One relies on using a secondary loop that has bigger transistors. The LDO reaches steady state faster than the main loop due to the higher adjustment steps. The other component controls the operating frequency by altering the REQ-ACK protocol in order to sample and update the output faster. The circuit was simulated and fabricated using Infineon's proprietary 130nm BCD technology and was assembled in SSOP-14 plastic package. Also, the proposed circuit was measured and the results show more than 50 percent improvement and a settle time reduction with a factor of 4 on sudden load changes while a light increase in output voltage ripple for steady-state operation must be considered.
This work brief a noninverting Schmitt trigger circuit with improved noise immunity. The work integrates the investigation of the proposed dual threshold controlled Schmitt trigger (DTC-ST) in terms of low switching power consumption, less propagation delay, and reduced leakage power. Thus, the end result of the proposed DTC-ST yields well-defined hysteresis behavior and better noise immunity due to the use of one PMOS and one NMOS as a two-layered feedback approach which can be employed in the low-noise receiver and waveform reshaping circuit applications. The DTC-ST has $2.89\times, 1.64\times$, and $4.9\times$ less delay, dynamic power, and leakage power respectively in comparison to the conventional Schmitt trigger. Further, 5000 Monte Carlo simulations reveal that low variation in $\mathrm{V}_{\mathrm{LH}}$ and $\mathrm{V}_{\mathrm{HL}}$ of the proposed circuit makes it a robust design.
A multifunctional transceiver for radar sensing and wireless communication (RadCom) has proven to be a valuable alternative to single-function transceivers as it enables system miniaturization and cost reduction. The use of a RadCom system for hand gesture recognition and data synchronization in smart-phones could further advance smartphone development to attain another level of miniaturization. However, power consumption remains a significant concern in these applications. This paper presents a low power RadCom architecture based on a 1-bit comparator, for high resolution sensing and high data rate communication. The transmitter is able to generate IR-UWB pulses and ASK symbols. The simulation results show that data transmission can be implemented up to 5 Gbps and within a range of a few cm. The results also show that the 1-bit comparator architecture can identify three out of five fingers of the hand and accurately translate the propagation channel scenario into the range Doppler map (RDM).
This paper presents an integrated soft start-up circuit implemented in a $0.5-\mu m$ GaN on Si technology suitable for on-chip integration in power applications. The proposed approach avoids the use of large on-chip or external capacitors to overcome the problem of voltage overshoot and inrush current at start up in switching power converters. It could be also adapted to the specific application by choosing the number of Flip Flops, or, for large start-up periods, using a counter, and setting the desired start-up signal duty cycle. Moreover, an optimized Flip Flop circuit topology has been proposed to reduce area occupation. The circuit working principle and the design challenges in GaN technology are discussed together with simulations. The circuit has been designed by considering worst-case conditions. A test buffer has been also included to drive the high external load capacitance of the readout device. Measured waveforms are reported that demonstrate the effective circuit operation and suitability for all-GaN integration.
This paper presents a strategy for performing noise analyses in a boost converter with Voltage Mode Control (VMC). The proposed analysis is particularly powerful when each of the power regulator transfer functions is known. The approach is demonstrated by injecting a noise source, treated as a single sinusoidal tone, in two scenarios: within and beyond the first Nyquist band. The effectiveness of the model is verified by comparing the calculated gains through FFT (Fast Fourier Transform) of the output voltage with the ones computed from AC analysis.
This paper introduces a 20 GHz multi-core digitally controlled oscillator (DCO) designed for high-speed and high-precision radar applications. The multi-core architecture provides superior output power, lower phase noise, and better stability compared to a single-core oscillator. Fabricated using a 28nm CMOS process, the oscillator comprises four identical cores and exhibits excellent phase noise performance, with a value of −118 dBc/Hz at 1 MHz offset from 19.5 GHz, 18% tuning range and - 189.6 Figure of Merit (FoM).
The paper proposes a method for automated optimization of line driver pre-emphasis parameters by utilizing the measured transfer function (TF) of the channel. Pulseecho measurements are performed in which pulses with a given frequency and duration are transmitted into the channel and the amplitude of the resulting echo detected to evaluate frequency-dependent line loss. The echo amplitude is indirectly detected using transmit pulses with different amplitudes and a simple comparator-based circuit that detects when the echo amplitude exceeds a user-defined threshold. The result is used to estimate the cable loss, and the process repeated for different input frequencies to estimate the channel TF. The proposed estimation procedure is validated using a transistor-level implementation in 65 nm CMOS for data rates up to 1 Gb/s, channel losses up to 15 dB, and a receiver reflection coefficient of −20dB.
This paper presents the design of a fast-response reference current $(I_{FRR})$ source being the reference for the high-voltage output current sources of a gate shaping digital gate driver for Silicon-Carbide power MOSFETs. By shaping the switching waveform driving the power MOSFET, there are significant improvements regarding energy efficiency and electromagnetic compatibility obtainable. The maximum reference current for the output current mirrors of the gate driver is 44.7mA with a total output current of 5.6A. A maximum startup time of less than 50ns over process and mismatch variations and the full temperature range of $-40mA^{\circ}{C}$ to from $150^{\circ}C$ is achieved. The total current consumption is {4.12mA from 5V with a reference current of 44.7mA from 20V while operating. The turn-off current consumption is 0 mA from 20 V and the standby current consumption is 9.27mA respectively.
When designing oscillatory circuits, intuition about phase noise is often hindered by the complex underlying mathematics and proprietary device compact models. While these models are very accurate, their complexity (and sometimes encryption) can lead to a black-box behavior. For the investigation of circuit topologies regarding noise it is desirable to work with more accessible, general compact models, decoupled from a specific technology node. We investigate how differences in compact model accuracy influence the simulation results of phase noise properties. For two exemplary circuits phase noise properties are calculated using a highly accurate foundry model and a simple SPICE level 1 model. Comparison shows that qualitatively correct results can be expected even for the simple compact model, especially when the susceptibility of oscillator phase as a function of time is investigated. However, simulations of statistical properties (e.g. the phase noise spectrum) are based on a fragile balance of positive and negative phase contributions, and are shown to vary more severely for different models.
This paper is a feasibility survey of the design of an oscillator-based bio-sensor for skin physiological parameter detection. The sensor aims to detect stress through skin sweating measurement. The proposed architecture uses an oscillator coupled to an on-skin resonator. The oscillator is based on a cross coupled pair (CCP) which is directly connected to the resonator. The on-skin resonator has been designed to have an oscillation frequency sensitive to the sweat. Oscillator outputs are driven by two buffers that act as 50 $\Omega$ impedance matching. Two test benches, one with a dry skin and one with a wet skin, have been used for the study. The oscillation frequency of this oscillator is equal to 27.876 GHz for the dry skin, and 27.911 GHz for the wet one. The difference between the two oscillation frequencies, which is equal to 35 MHz, can be easily distinguished which validates the feasibility survey. The survey provides the sizing of each block and the simulated results in 55 nm BiCMOS technology.
