The most required task is to make the smart application more smart-able, offering the security constraints for the Internet of Things (IoT). Several cryptographic models, such as Rivest Shamir, blowfish, advanced encryption standard (AES), etc., have already been implemented to offer Security for IoT applications. However, security modules are not sufficient for handling information from third parties. So, the present study has introduced a novel Boolean Two Fish Crypto Security Framework (BTFCSF) in the Very Large Scale Integration (VLSI) chip. The main objective of this study is to design an efficient Twofish model by combining the Boolean feature in the Twofish algorithm. Finally, the designed model was tested in the Xilinx vertex ultra scale+ platform, and the performance was compared with other Xilinx families and other traditional crypto models. The VLSI performance metrics, such as Flipflop, frequency, dynamic power, static power, and time, were measured, in that the proposed model in Virtex UltraScale+ scored the finest performance as reduced power consumption 98mW dynamic power and 30mW static power were received. In addition, the IoT performance was also justified by attaining the 87Gbps throughput ratio, which is better than other family devices.
Fault tolerance remains a paramount challenge in scaling Networks-on-Chip (NoCs) as multi-core systems grow in complexity and size. As 3D NoC architectures scale to support hundreds of cores, the probability of encountering both transient and permanent faults within routers and vertical Through-Silicon Vias (TSVs) increases significantly, threatening system reliability. To mitigate these fault-induced reliability threats, this paper proposes the Adaptive Tiled-Layer Architecture for Scalability (ATLAS), a novel hierarchical routing framework designed for 3D NoC systems. ATLAS integrates the sustained reliability of wired interconnects with the low-latency advantages of wireless shortcuts to dynamically optimize data flow in the presence of faults, network congestion, and thermal variations. The proposed methodology theoretically decouples high-level path planning from low-level obstacle avoidance. A global Network Interface (NI) executes strategic path selection, while a local Routing Decision Unit (RDU) facilitates hop-by-hop adaptive navigation. Extensive evaluations conducted using the Access Noxim simulator reveal that ATLAS maintains robust operational stability and high throughput comparable to fault-free conditions under 1
SRAM-based field-programmable gate arrays (FPGAs) are increasingly used in relay protection and other safety-critical digital systems because of their flexibility and high integration. However, their configuration memory is vulnerable to neutron-induced single-event upsets (SEUs), which may lead to persistent logic errors and long-term reliability degradation. This study evaluates a configuration-memory soft-error mitigation approach based on a vendor-provided SEM/SEU IP core implemented on a PANGO LOGIC PG2L100 SRAM-based FPGA. Atmospheric-like neutron irradiation experiments were conducted to quantify configuration upset behavior, single-event cross-sections, and projected soft error rates (SERs) with and without mitigation. Without mitigation, 434 and 448 configuration upset events were observed in two irradiation rounds at fluences of 2.56 × 109 and 2.68 × 109n/cm², respectively, corresponding to an estimated cross-section of approximately 1.68 × 10− 7cm². With the SEM function enabled, no residual uncorrected single-bit upsets were recorded over ten irradiation rounds with a total fluence of 1.738 × 109n/cm2, while two residual multi-bit upset events were observed, yielding an estimated cross-section of approximately 1.15 × 10− 9cm². Using a terrestrial reference neutron flux defined over the same En>1 MeV energy range as the measured cross-sections, the projected SER of PG2L100 decreased from approximately 2486 FIT to 17 FIT after mitigation. This comparison reflects the reduction in residual uncorrected configuration upsets achieved by SEM-based mitigation rather than a direct comparison of identical event categories. The results demonstrate that configuration-level SEM provides an effective and low-overhead reliability enhancement strategy for SRAM-based FPGAs used in relay protection applications, although residual multi-bit upsets still require system-level recovery mechanisms.
As semiconductor manufacturing becomes increasingly outsourced to untrusted entities, Hardware Trojan (HT) attacks pose a critical threat to the security and reliability of modern integrated circuits. Machine learning models have improved the effectiveness of HT detection using Ring Oscillator Network (RON) side-channel data, yet recent work shows that these models are highly vulnerable to adversarial attacks. This paper evaluates the robustness of the Support Vector Machine (SVM) classifier, a leading algorithm in state-of-the-art HT detection frameworks, under gradient-based adversarial attacks. The proposed work demonstrates that high nominal accuracy does not ensure security against these attacks, which can reduce recall to zero. To strengthen resilience, three data-augmentation methods are investigated: SMOTE, Conditional Tabular Generative Adversarial Network (CTGAN), and Tabular Variational Autoencoder (TVAE). TVAE produces high-fidelity synthetic samples and substantially improves robustness, maintaining over 91
Hardware trojans are malicious circuits which compromise the functionality and security of an integrated circuit (IC). These circuits are manufactured directly into the silicon and cannot be fixed by security patches like software. The solution would require a costly product recall by replacing the IC and hence, early detection in the design process is essential. Hardware detection at best provides statistically based solutions with many false positives and false negatives. These detection methods require more thorough explainable analysis to filter out false indicators. Existing explainability methods developed for general domains like image classification do not always provide the actionable insights hardware engineers need. A question remains: how do domain-aware property analysis, model-agnostic case-based reasoning, and model-agnostic feature attribution techniques compare for hardware security applications? This work compares three categories of explainability for gate-level hardware trojan detection on the Trust-Hub benchmark dataset: (1) domain-aware property-based analysis of 31 circuit-specific features derived from gate fanin patterns, flip-flop distances, and primary Input/Output (I/O) connectivity; (2) model-agnostic case-based reasoning using k-nearest neighbors for precedent-based explanations; and (3) model-agnostic feature attribution methods (Local Interpretable Model-agnostic Explanations (LIME), SHapley Additive exPlanations (SHAP), gradient) that provide generic importance scores without circuit-level context. The findings show that different explainability approaches offer distinct advantages for hardware security practitioners. The domain-aware property-based method analyzes 31 circuit properties. Detection decisions are explained through familiar concepts like “high fanin complexity near outputs indicates potential trojan triggers.” Case-based reasoning (k-nearest neighbors) achieves 96.51 ρ = 0.30 mean over n = 11,392 gates, 95 [0.29, 0.31] ; global concatenated ρ = 0.31 , p ≪ 10^-300 ), and yield generic feature importance scores that lack circuit-level context for validation or remediation planning. Detection performance using eXtreme Gradient Boosting (XGBoost) classification with optimized threshold achieves 48.08
Scan chains introduced by design for testability (DFT) significantly enhance testability but also expose internal circuit states to scan-based attacks. To address this vulnerability, this paper proposes a secure scan architecture based on hidden authorization and dynamic data replacement. The hidden authorization mechanism emphasizes stealth by concealing the authentication process itself, avoiding explicit key storage, comparison, or observable feedback, thereby preventing attackers from inferring authorization states or triggering conditions. In addition, a new nonlinear feedback shift register (NLFSR) is proposed to generate substituted scan data under unauthorized access. Unlike conventional LFSR-based schemes, the proposed NLFSR employs a highly nonlinear feedback structure, achieving enhanced nonlinearity and strong resistance to algebraic attacks while improving the unpredictability of replacement data. Furthermore, a new replaced critical scan flip-flop (RCSFF) structure is introduced. By relying on the systematic definition and precise localization of critical scan nodes (CSNs), the RCSFF dynamically replaces security critical scan data, effectively disrupting sensitive information leakage without compromising scan functionality. Experimental results demonstrate that the proposed architecture significantly improves resistance to scan-based attacks with low hardware overhead and no impact on test time.
The increasing reliance on third-party intellectual property (IP) cores, coupled with the globalization of the semi-conductor manufacturing process, has raised significant security concerns in the design and deployment of modern integrated circuits (ICs). One of the most insidious threats in this domain is the insertion of Hardware Trojans (HTs), malicious modifications, or additions to the design of a circuit that can compromise its functionality, leak sensitive information, or render it vulnerable to external attacks. Creating efficient test patterns capable of identifying these anomalies, particularly in the midst of noise and the vast design space of contemporary integrated circuits, continues to be a significant challenge. This paper presents a novel hybrid approach that integrates particle swarm optimization (PSO) and reinforcement learning (RL) to generate optimized test patterns aimed at enhancing rare-gate activation and Trojan-trigger activation. Experimental results in ISCAS’85 and ’89, and ITC’99 benchmark circuits demonstrate that the proposed PSO-RL approach outperforms traditional heuristic methods, including MERO and TRIAGE, in terms of both average fitness and trigger coverage. Comparative analysis with standard PSO reveals that integrating RL yields improved trigger activation, particularly for complex circuits such as AES-128 from MIT-CEP and under hard-trigger conditions, thereby supporting its scalability.
Printed Circuit Boards (PCBs) are fundamental components in nearly every electronic system, ranging from consumer products to space applications. Due to the sophistication and miniaturization of modern PCBs, fault-free production is critical. Manual inspection and image-processing- based methods in the early stages are typically not adequately efficient in terms of speed, precision, and scalability. With advancements in deep learning, particularly object detection models, the YOLO (You Only Look Once) family of models has emerged as one of the top real-time contenders in PCB defect inspection. This paper provides a detailed discussion on the progress of lightweight models from the YOLO family in PCB surface defect detection. It discusses the working principles of YOLO, its advantages in industrial inspection, and summarizes recent variants such as YOLO-WWBI, SCF-YOLO, GESC- YOLO, and AE-YOLO. These frameworks attempt to achieve a trade-off between detection accuracy and computational cost, making them suitable for deployment in edge and embedded devices. By comparing their architectural innovations, detection abilities, and applicability in real-world settings, this paper provides insights into emerging trends and recommends directions for future research on intelligent, real-time PCB inspection.
Built-In Self-Repair (BISR) methods and Error Correction Code (ECC) are commonly employed to enhance the yield and reliability of NAND flash memories. However, the robust error correction capabilities are not fully utilized to protect the memory throughout its entire lifespan. Additionally, while redundancies are essential for improving manufacturing yield, the effectiveness of spare usage is often limited due to the requirement for high-granularity spare blocks and columns. To address these challenges, this paper proposes a built-in ECC repair (BIER) technique by resequencing ECC and BISR. With BIER, a user-defined number of codewords allocate a portion of the ECC’s error correction capacity to repair random manufacturing defects. This approach significantly reduces dependence on spare components, as the distribution of manufacturing defects is more amenable to ECC-based repair. We also continuously monitor the correction slack (CS) of codewords during ECC decoding. If the CS falls below a specified threshold, the correction capability for those codewords is enhanced. The additional BIER circuitry can be utilized to store extra check bits. Consequently, the yield and reliability of flash memory can be substantially improved with fewer spares and reduced ECC overhead. We also details the corresponding test and repair process. Experimental results demonstrate that the proposed BIER technique significantly enhances flash memory yield and reliability with minimal hardware cost.
It is significant for the radiation hardened techniques to measure the pulse width of single event transient (SET), which has become one of the most important reliability issues of integrated circuits (ICs). Based on Vernier Delay Line topology, an autonomous pulse width measurement system is designed. It is composed of delay propagation circuit, SET capture circuit and output register circuit. The accurate result of the SET width is achieved by the mean value of uniform distribution instead of the number of triggered stages. To validate and test the proposed design, the measurements of the pulse widths from different linear energy transfer (LET) heavy-ion exposures are performed. The results show that the proposed design can obtain the pulse width accurately and multiple transient can be also captured. Results from 1000 random cases show that by comparison with the previous test circuit, the proposed design has a significant improved accuracy with an average error of only 1.19
This paper proposes a discrete-component-based Built-Out Self-Test (BOST) architecture incorporating a high-precision Time-to-Digital converter (TDC) to overcome limitations of high-speed device testing system. The rapid advancement of Wide Bandgap (WBG) power devices—particularly Gallium Nitride (GaN) devices featuring ultra-fast switching characteristics such as 10 ps/V fall-time behavior—has created new challenges for mass-production testing. Conventional Automated Test Equipment (ATE) often lacks sufficient timing accuracy and suffers from signal degradation due to the physical separation between the tester and the device under evaluation, making sub-nanosecond measurements unreliable. We introduce a Vernier SAR TDC that achieves an effective timing resolution of 1 ps, not by relying on traditional delay-line interpolation but by injecting a Gaussian-distributed dither (GDD) into the comparator threshold voltage ( V_th ). This controlled noise, generated on-chip by a microcontroller unit (MCU) implementing the Box–Muller transform, statistically subdivides the coarse 10 ps quantization step to realize a fine-resolution “vernier scale.” Experimental validation using a commercial GaN gate driver IC (BD2311NVX-LB) confirms that the proposed method accurately measures rise times and ultra-short pulse widths with 1 ps resolution and sub-1 ps variation. The results demonstrate that GDD-assisted Vernier SAR TDC significantly enhances timing linearity and mitigates nonidealities such as comparator propagation delay variation. This cost-effective and scalable BOST solution provides a practical pathway for high-volume, picosecond-class testing of next-generation high-speed power devices, serving as an alternative to full-custom ICs.
The design of RadioFrequency (RF) cryogenic circuits has attracted much interest in recent years due to applications such as quantum computers. Interface electronics with ultra-low levels of power consumption at temperatures as low as 4 K are required. Silicon technologies are being considered for implementation because of the possibility of large-scale qubit integration with energy-efficient readout and control interfaces. However, the design of RF cryogenic circuits is complicated because of the lack of standard design kits with the corresponding component models for their simulation at these temperatures. Alternative approaches to avoid costly design and fabrication cycles are possible, in particular the use of Look-Up-Table (LUT)-based techniques that exploit characterization data of circuit components at cryogenic temperature. In this paper, we make use of this approach for the design of a RF Low Noise Amplifier (LNA) using a 28 nm FD-SOI technology that has been characterized at cryogenic temperatures using DC measurements. Furthermore, we also experimentally demonstrate that the DC measurements used are valid to extract the transistor noise parameters used in the LUT-based analysis.
In the evolving landscape of hardware security, safeguarding intellectual property (IP) at the gate level remains a persistent challenge. This work presents a unified approach to watermarking both RTL and synthesised netlists, addressing the growing need for robust, traceable, and non-intrusive IP protection. By integrating graph neural networks (GNNs) to intelligently identify watermark insertion points, the method bridges a critical gap between functional preservation and security resilience. Unlike existing solutions that compromise either stealth or synthesis integrity, this approach ensures verifiable watermarking with minimal area overhead while maintaining circuit functionality, paving the way for trustworthy and scalable IP protection mechanisms in VLSI.
With the continuous development of technology, the integration degree of transistors is rapidly increasing, making SRAM (Static Random Access Memory) cells employed in aerospace applications more susceptible to soft errors. High-energy particles striking sensitive nodes of semiconductors can cause single-event upset (SEU), affecting stored data. To address this, we introduce a 14-transistor LRDLAP cell designed for low-read delay and power consumption, which effectively mitigates the impact of SEU. Compared to recent SRAM cells with soft-error detection capabilities, the LRDLAP 14T cell achieves the fastest read access time, minimum average power consumption, and superior write capability. Specifically, it reduces average power consumption by 31.10
Three-dimensional stacked memory architectures provide high bandwidth and density while exhibiting increased susceptibility to radiation-induced single-bit upsets and clustered multi-bit upsets. Traditional Hamming-based error-correcting codes offer narrow fault protection. This work proposes an extended multi-region Hamming-based ECC that incorporates redundant bits for each row, column, and diagonal, enhancing resilience to multi-bit errors in both 2D and 3D memories. The approach is evaluated by using exhaustive fault-injection analysis. To assess the ECC’s performance, 30,000 randomly generated fault cases were evaluated by injecting 1 to 12 errors, and were compared to previous works. The proposed ECC consistently outperforms existing works, achieving 90
This paper presents an ultra-broadband on-chip bias network for distributed amplifiers (DAs) in indium phosphide (InP) technology, eliminating conventional RF-choke constraints through a reconfigurable 2-port DC-feed block. Capitalizing on distributed amplification principles, the reverse-configured topology with strategic port inversion grounds RF pathways while integrating an R-C impedance network (50- Ω resistor + 0.2-pF capacitor) to suppress power supply noise and enable native cascadability. Measured results demonstrate ultra-broadband operation with >10 dB isolation from 20 to 170 GHz in a compact size of 0.015 mm ^2 . Crucially, the proposed architecture eliminates external bias-tee modules by providing on-demand reconfigurability, and the direct RF-port connection evolves the DC-feed into a fully operational 3-port bias-tee, unlocking monolithic integrated circuits (MMICs) and sub-terahertz (sub-THz) wireless applications. This architecture optimizes noise suppression, test complexity, and functional flexibility, establishing another topology for integrated bias networks.
Wafer manufacturing plays an important role in semiconductor industry, which requires high precision and complicated processes, and defects are inevitable in manufacturing. Wafer map defects show different image features due to their formation, the shape, size, and distribution position of defects are random, which limits the effectiveness of traditional machine learning detection. In order to improve the accuracy of wafer map defect pattern recognition and improve the ability to identify wafer map defects, this paper conducts research on wafer map defect pattern recognition based on the ResNeSt method with the multi-attention mechanism and enhanced activation function. The Hswish-ResNeSt50 network is generated by modifying the activation function in the ResNeSt network, which improves the accuracy of wafer map defect recognition. By introducing the CBAM and the self-attention mechanism between the convolutional layers of the Hswish-ResNeSt50 network, three methods for adding the CBAM and the self-attention mechanism are designed, namely: introducing CBAM between the network’s convolutional layers to design the Hswish-ResNeSt50-LC(LC) network; introducing the self-attention mechanism between the network’s convolutional layers to design the Hswish-ResNeSt50-LS(LS) network; introducing both CBAM and the self-attention mechanism between the network’s convolutional layers to design the Hswish-ResNeSt50-LCS(LCS) network. Experimental results show that the above methods can effectively improve the ability of the network to recognize wafer map features. Among them, Hswish-ResNeSt50-LC3, Hswish-ResNeSt50-LCS3 and Hswish-ResNeSt50-LCS4 have the best effect by introducing attention mechanism in different convolutional layers of Hswish-ResNeSt50 network. The accuracy of these three network reached 98.21
Phishing attacks have become increasingly sophisticated and remain one of the most prevalent threats to online security, leading to significant financial losses and privacy breaches. Despite the progress of machine learning-based detection systems, many existing approaches still suffer from limitations such as high-dimensional feature spaces, redundant URL attributes, and severe class imbalance in phishing datasets, which reduce detection accuracy and increase false alarm rates. To address these challenges, this study presents a comprehensive and practical framework for phishing URL detection by integrating a large, diverse real-world dataset, advanced feature engineering, and hybrid machine learning and deep learning models. Structural features are extracted from URL parameters, suspicious keyword patterns, and host structure to capture both lexical and behavioral characteristics of phishing attempts. To mitigate dataset imbalance, the Synthetic Minority Oversampling Technique (SMOTE) is applied to improve model training. Furthermore, a binary Sand Cat Swarm Optimization (SCSO) algorithm is employed for feature selection to identify a compact and informative subset of features. Experimental results demonstrate that while several classifiers perform reasonably well without feature selection, others struggle with the high-dimensional feature space. After applying SCSO, all classifiers exhibit significant improvements in accuracy, precision, sensitivity, F1-score, and AUC. Among the evaluated models, LSTM achieves the strongest overall performance, with AUC values approaching 0.98 and consistent stability across cross-validation folds. The results confirm that SCSO effectively removes redundant and noisy features, enhances generalization capability, and reduces false alarms. Overall, the proposed framework significantly improves detection accuracy, AUC, and adaptability across diverse phishing attack patterns, making it suitable for practical real-world deployment.
As the semiconductor technology advances, soft errors caused by radiative particles are becoming a major concern for power-sensitive digital circuits in aerospace applications. Radiation hardening by design (RHBD) and magnetic tunnel junction (MTJ) are employed to cope with these issues. In this paper, two novel non-volatile flip-flops (FFs) are proposed, both of which can fully recover from all single- and double-node upsets (DNUs). The embedded MTJs are non-volatile and compatible with the conventional CMOS process. Comprehensive simulations show that the proposed flip-flops have excellent DNU-recovery and non-volatility at the cost of a low increase in area overhead. The proposed flip-flops reduce the delay by 21.99
The paper provides new tables of primitive polynomials of degree 661 through 1200 over the Galois field of 2 elements. These polynomials meet requirements of ring generators – a class of linear feedback shift registers with enhanced structural and functional properties compared to their conventional counterparts. For each degree polynomials with 7, 9, and 11 coefficients are given. The coefficients are separated from each other such that the resulting implementations are highly modular.
