Battery-powered IoT sensor nodes require energy-efficient Medium Access Control (MAC) protocols to extend network lifetime while supporting priority-sensitive traffic. This paper proposes a Priority-Aware Packet Aggregation/Piggybacking-Based (Priority + Packet Aggregation) Hybrid Energy-Efficient MAC (P2A-HMAC) protocol that integrates bit-mapped priority signaling with lightweight packet aggregation/piggybacking to reduce control overhead. The protocol classifies traffic into emergency, buffer-overflow, priority, and normal categories, providing guaranteed access to delay-sensitive data while minimizing radio activity, idle listening, and contention. A mathematical energy model is developed for both priority- and contention-based operations. MATLAB-based evaluation demonstrates that P2A-HMAC consistently achieves lower energy consumption than TDMA, EA-TDMA, ASHMAC, E-BMA, and P2A-HMAC across varying network sizes, packet sizes, and event-generation probabilities. The proposed protocol provides substantial energy savings, particularly in large-scale and moderate-traffic networks, while maintaining priority-aware communication and QoS, making it suitable for low-power IoT and wireless sensor network applications.
In this work, a plasma-free atomic layer deposition (ALD)-based H2O post-treatment method is proposed to precisely modulate hydrogen-related (H-related) traps in indium gallium zinc oxide (IGZO) thin-film transistors (TFTs) by the number of H2O treatment cycles. Under the optimized condition, the scaled device with a channel length of 70 nm exhibits a near-ideal subthreshold swing of 62.9 mV/dec, a low threshold voltage (VTH) of 0.18 V, an acceptable static leakage current, and a high drive current of 3.29 μA/μm at an overdrive voltage and drain voltage of 1 V. In addition, the treated device shows only a 13 mV of VTH shift after 1000 s positive bias stress (PBS), corresponding to a 94% improvement compared with the pristine device. These improvements are attributed to the introduction of two different polarities of hydrogen-related traps after H2O treatment. Furthermore, the influence of H-related traps on bias stability and the mechanisms responsible for VTH shift are systematically clarified. These results establish that an optimized hydrogen incorporation window that maximizes the beneficial effects while balancing severe hydrogen-induced degradation caused by excessive hydrogen incorporation. Consequently, scaled IGZO TFTs with fast switching, low-power operation, high performance, and high reliability can be achieved, providing strong potential for back-end-of-line (BEOL)-compatible electronics and monolithic three-dimensional integrated applications.
This paper proposes a sensorless current estimation method for piezoelectric energy harvesting (PEH) systems using a first-order Takagi–Sugeno fuzzy system. Unlike invasive current sensing, the proposed estimator uses only non-invasive measurements: output voltage VO, its derivative V˙O, and load resistance RL. The fuzzy rules are initialized directly from the physical equivalent circuit parameters and trained via the ANFIS on a large-scale dataset (78 million samples). The proposed model achieves a mean coefficient of determination R2=0.9999 (95% CI: [0.99989, 0.99991]), root mean square error RMSE=3.12×10−8 A, mean absolute percentage error MAPE = 2.51% (95% CI: [1.98, 3.04]%), and fitness FIT = 98.98%—outperforming multiple linear regression (R2=0.9738 and MAPE = 116.25%) and a shallow neural network with 211 parameters (R2=0.9991 and MAPE = 13.85%) despite having only 170 trainable parameters. Unlike black-box neural networks, the fuzzy model provides interpretable rules whose consequent parameters map directly to physical quantities (effective capacitance Cp(eff) and leakage conductance 1/Rp(eff)). The low computational footprint (170 parameters, <5 μs inference, and ≈1.4 kB of memory) makes it suitable for real-time deployment on low-power microcontrollers. These results demonstrate the viability of the proposed approach under controlled laboratory conditions for the single, series, and parallel PEH configurations considered. This work establishes that physically informed fuzzy modeling is a viable, interpretable, and efficient alternative to deep learning for sensorless monitoring in low-power energy harvesting systems.
This paper presents a low-power fully integrated sine signal generator for on-chip bioimpedance spectroscopy applications. The circuit is based on a relaxation oscillator, which generates a triangular signal, followed by a sixth-order Gm-C bandpass filter (BPF) that linearizes the waveform. Both blocks, designed in a 0.18 μm CMOS process with 1.8 V supply, make use of a current division technique to generate low-frequency signals without requiring high-valued passive components. The relaxation oscillator features an extended frequency tuning range from 300 Hz to 300 kHz, controlled via a tuning current and a digital capacitor bank. The sine output waveform spans from 1 kHz to 50 kHz, and exhibits a −48.8 dB total harmonic distortion at 10 kHz with 18 mV amplitude. The overall system area is 0.7 mm2 and the power consumption is lower than 30 μW.
Edge inference on resource-constrained embedded nodes demands accelerators that are energy-efficient and compact. This paper presents Versat-AI, an open-source compiler that accepts a standard Open Neural Network Exchange (ONNX) model and generates a complete, synthesisable RISC-V System-on-Chip (SoC) with an embedded CGRA accelerator. The key innovation is applying a known hardware merge strategy to collapse structurally compatible neural network operators into a physical CGRA instance. The Versat-AI compiler also derives memory-mapped interconnects, firmware drivers, and RISC-V application software co-generated by the Py2HWSW SoC framework, eliminating the manual hardware/software co-design effort that previously tied this accelerator’s own design lineage to a single target network. The next phase of the project is to extend this same automatic derivation from sizing the operator vocabulary to sizing per-operator parallel instancing and bandwidth, following the bandwidth-matched scaling principle already demonstrated, by hand, in this accelerator’s own design lineage. The current phase of the project has succeeded in creating a sound automation flow that produces an accelerator that maps each operator onto a single physical datapath instance and occupies 8763 LUTs, 9833 flip-flops, 4 DSPs, and 202 BRAMs on a Xilinx Kintex UltraScale field-programmable gate array (FPGA)—a footprint unchanged across all evaluated models regardless of size—and draws 0.65 W (1.96 W for the complete SoC including the DDR4 controller, by Vivado post-implementation power estimation), achieving 2.3× to 9× speedup over the software-only baseline produced by the same flow on four MLPerf Tiny benchmark tasks. The paper further examines the design choices that delimit this first phase—single-precision arithmetic, a single datapath instance per operator, and the block-RAM cost of the accelerator’s streaming buffers—and sets out the path to quantised integer support and parallel operator instancing. A condensed account of the two-decade lineage of reconfigurable accelerators and open-source SoC platforms that motivated Versat-AI’s design is also given.
The measurement of the magnetic field generated by a flowing current constitutes a non-invasive sensing technique for online energy consumption monitoring. In this work, based on the use of low-cost linear Hall effect sensors, a low-form-factor custom contactless ammeter probe is presented. The differential configuration of the sensor module and the subsequent fully digital programmability in range and sensitivity, together with the included self-calibration and compensation circuits for mismatching, managed by a microcontroller, allow for optimum detection for both continuous and mains current with a resolution of 10 mA for input ranges of 2 A. The proposed ammeter power consumption and measurement accuracy in different scenarios are tested, including the power monitoring of an IoT-based device, obtaining results matched to those featured by a commercial oscilloscope current probe, which validates its suitability and reliability as autonomous low-cost probe for portable contactless power monitoring.
The increasing demand of digital technologies and their integration with wearable health devices provides an efficient trigger for next-generation wearable healthcare devices for long-term physiological monitoring. The advancement of energy harvesting mechanism, nanomaterial-based sensor fabrication and their integration with digital technologies have emerged as a promising solution for transforming future of digital health. This study provides a comprehensive summary and framework for wearable self-powered electronic devices, enabling continuous, battery-free health monitoring and advancing the development of sustainable, next-generation digital healthcare systems. This review paper presents a broad and detailed overview of current technologies and sensors advancement in developing low-power wearable, self-powered electronic devices suitable for healthcare applications. The importance and reliable use of key energy harvesting approaches including triboelectric, piezoelectric, thermoelectric, and photovoltaic approaches are systematically presented which focused on development of energy efficient wearable devices. This review further examines the low-power circuit design strategies for flexible electronics focusing personalized healthcare monitoring. Current challenges and limitations related to advanced manufacturing of wearable health devices focusing on large-scale deployment are also analyzed. Finally, the key future research directions are outlined for advancing a next-generation intelligent digital health system.
The rapid growth of Deep Neural Networks (DNNs) has led to the development of application-specific DNN accelerators. Conventional 2D von Neumann architectures suffer from memory bandwidth limitations between the memory and the processing core. 3D DNN accelerators have emerged as a promising solution by leveraging 3D integration to enable near-memory logic or in-memory computation. By shifting computation closer to memory, these accelerators significantly reduce data movement and therefore latency, resulting in more energy-efficient operations. Monolithic 3D (M3D) integration, in particular, enables high-bandwidth systems by utilizing high-density monolithic inter-tier vias (MIVs). This paper provides a critical review of recent advances in 3D DNN accelerators that combine near-memory and compute-in-memory with various 3D technologies, offering a useful discussion and future prospects of the available technologies and architectures that have advanced the performance of DNN accelerators. Particular attention is devoted to accelerators for emerging transformer-based large language model (LLM) networks due to the higher memory demands. Thermal-aware design techniques of 3D DNN accelerators are also discussed as a means to address the fundamental challenge of heat dissipation. A detailed review is finally conducted on package-level constraints, considering signal integrity, power delivery, and thermo-mechanical reliability.
High penetration of renewable energy sources (RESs) introduces significant power fluctuations, threatening voltage and frequency stability in modern power systems. This paper presents an integrated framework for static voltage stability assessment and stability-constrained optimization of under-frequency load shedding (UFLS) in renewable-dominated grids. A low-conservativeness analytical criterion is first derived for static voltage stability margin assessment. Then, a hybrid Deep Belief Network-Long Short-Term Memory (DBN-LSTM) model is developed for accurate renewable power forecasting, capturing temporal variability and uncertainty. Finally, UFLS-based stability-constrained dispatch is formulated to prevent voltage collapse, enhance the system stability, and minimize RES curtailment. Simulations on a modified IEEE benchmark system demonstrate that the proposed approach improves voltage and frequency stability while maintaining high renewable energy utilization.
This paper presents the design and implementation of an X-band voltage-controlled oscillator (VCO) fabricated in a standard 180-nm CMOS process. To sustain stable oscillation under a constrained power budget, a gm-boosted topology is employed, integrating vertically stacked cross-coupled transistors with a center-tapped transformer to enhance the equivalent negative conductance. The boosting is achieved through two complementary mechanisms: the center-tapped transformer performs an impedance transformation that repurposes the layout parasitic capacitances into transconductance-enhancing elements, while the stacked cross-coupled pair reuses the DC current and suppresses the source-degeneration of a conventional pair, jointly sustaining a robust start-up margin at a low 0.75 V supply. On-wafer measurement results demonstrate a frequency tuning range from 8.78 GHz to 9.13 GHz as the control voltage is swept from 0 V to 1.8 V, with an average VCO gain KVCO of 447.5 MHz/V. Under a total DC power consumption of 6.9 mW, the oscillator delivers an output power of 4.54 dBm and exhibits a measured phase noise of −103 dBc/Hz at a 1-MHz offset.
This paper provides a comprehensive analysis of active frequency doubler architectures adopted for efficient generation of millimeter-wave (mm-wave) signals. The operational principles of each topology are explained to address a thorough comparison based on essential performance metrics such as conversion gain, power efficiency, and spectral purity. The review covers several topologies from the standard push–push (PP) doubler to its power-efficient evolution, the complementary push–push (CPP) doubler. Furthermore, this paper focuses on more recent and advanced topologies, including the complementary common gate capacitive cross-coupled (CCGCCC) doubler. Finally, this work proposes and evaluates an improved version of the CCCGCC doubler, offering insights into the state of the art and future directions in mm-wave frequency multiplication.
A 0.3 V nanowatt CCII− is presented in 0.18 μm TSMC CMOS, targeting ultra-low-power current-mode interfaces. Post-layout extracted simulations demonstrate correct conveying operation with a total DC power consumption of less than 2.40 nW. The low-frequency tracking factors evaluated at 1 Hz are β0=0.9452 (−0.48 dB) and α0=0.9609 (≈−0.35 dB), with −3 dB bandwidths of 22.95 kHz and 63.95 kHz for the voltage and current transfers, respectively. Small-signal extraction confirms the intended impedance profile, yielding RX=46.73 MΩ, RZ=1.204 GΩ, and a very high input resistance RY=392 GΩ. Robustness is verified through full PVT and mismatch analyses, showing stable functionality across process corners, a 0–80 °C temperature range, and 270–330 mV supply variations while maintaining nanowatt-level dissipation.
Distributed energy systems open up a vast field of research in power electronics. Local solar power generation requires DC-DC converters that adapt the energy generated by the panels to on-site distribution buses. In addition, the control of the power converter to obtain the maximum possible energy from the solar source is crucial for the correct deployment of these distributed grids. In this work, system-level solutions are proposed for this application as follows: On the one hand, the use of novel resonant forward-flyback converters allows for a higher energy density than that of a conventional flyback and more relaxed withstand voltages on the switching elements. On the other hand, the implementation of maximum power point tracking algorithms for solar energy using Edge AI enables the deployment of algorithms that maximize the energy obtained locally. These improvements are shown by means of a prototype demonstrator, using cutting-edge microcontrollers and the implementation of a DC-DC power converter based on the proposed topology.
This paper introduces a novel analog-to-digital converter (ADC) employing a passive noise-shaping (NS) technique combined with a chopper-stabilized comparator, enhancing performance and reducing ripple factor while maintaining low power consumption. The NS architecture is built on a cascade-integrator feedforward (CIFF) structure, using both infinite- and finite-impulse response filters to minimize quantization and kT/C noise. Additionally, it employs a low-power two-stage chopper amplifier to compensate for the offset voltage and enhance system stability. Validated according to the 180 nm CMOS process, the proposed ADC has an effective number of bits of 10.6, a signal-to-noise-and-distortion ratio of 68.4 dB, and a signal-to-noise ratio of 59.33 dB. With a compact area of 0.17 mm2 and a power consumption of 650 µW from a 1.8 V supply, the proposal is well suited to biomedical sensor applications requiring strict accuracy and low energy consumption.
Accurate estimation of lithium-ion battery State of Health (SoH) is critical for emerging applications such as reconfigurable battery systems. Although data-driven machine learning methods are promising, they often rely on costly, time-intensive aging experiments and extensive feature engineering. This work proposes a lightweight SoH-prediction framework validated on both physics-informed synthetic aging data and the NASA battery aging dataset. We evaluated Random Forest (RF) and Feedforward Neural Network (FNN) models that use only a limited number of samples from an early segment of the raw discharge voltage curve as input. Results show that RF consistently outperforms FNN across input sizes in deterministic or noise-free environments, achieving an RMSE of 0.07% SoH using just 5 voltage samples. In inherently stochastic experimental data, however, FNN can achieve an RMSE 50% lower than RF (1.28 vs. 2.87), but requires 37× more mathematical operations per inference. These findings emphasize the predictive value of the early-discharge-voltage region and demonstrate that compact, low-feature-complexity models can deliver accurate SoH estimates. Overall, the approach supports a goal of combining informed synthetic data with limited real measurements to build robust, scalable SoH predictors, reducing dependence on labor-intensive degradation testing and feature-heavy pipelines.
AI accelerators increasingly operate under tight power, thermal, voltage, and timing margins, making workload-dependent thermal nonuniformity an important reliability concern. In systolic AI accelerators, localized activity concentration can create spatially uneven thermal stress, but thermal or timing-exposure analysis alone does not determine whether such stress remains benign, becomes numerically masked, or propagates into silent corruption. This paper presents a cross-layer early-stage screening methodology for thermal nonuniformity-aware reliability analysis in systolic arrays. The framework links workload-aware activity extraction, relative power concentration modeling, diffusion-based thermal proxy analysis, an explicit thermal-to-timing stress abstraction, path class-aware corruption modeling, and clean/masked/silent outcome classification. The revised framework is formalized mathematically and evaluated across dense, low-dynamic-range, and sparse GEMM workloads under weight-stationary and output-stationary execution. To strengthen statistical and methodological confidence, the study includes 100-seed corruption reruns with Wilson confidence intervals, thermal scaling across 8×8, 16×16, and 32×32 arrays, calibration sensitivity, path weight sensitivity, component ablations, and preliminary compact thermal reference alignment. The results show that sparse workloads consistently produce the largest thermal spread across tested array sizes, while dense and low-dynamic-range workloads remain more spatially uniform. Under the default calibrated screening regime at 16×16, sparse output-stationary and sparse weight-stationary cases reach 49% and 40% silent corruption rates, respectively, while dense cases remain mostly clean or masked and low-dynamic-range cases remain largely clean. Sensitivity and ablation experiments show that the sparse workload risk is not caused by one isolated modeling component, although the masked/silent split depends on path class weighting and thermal diffusion assumptions. The main contribution is not signoff-accurate silicon failure prediction, but a reproducible screening front end for identifying workload, dataflow, and path class combinations that deserve deeper thermal, timing, RTL-level, and application-level validation.
Analog in-memory computing (AIMC) has emerged as a promising approach to mitigate the Von Neumann bottleneck in matrix operations, which are common in deep learning applications. However, the practical implementation of resistive crossbar arrays is limited by challenges in signed weight representation, conductance quantization, and device nonlinearity. This paper presents a differential mixed-signal architecture for accurate signed matrix–vector multiplication (MVM), integrated with a RISC-V microcontroller for edge inference applications. A structured digital-to-analog mapping framework encodes quantized neural network weights into programmable conductance values while preserving arithmetic correctness. The design employs voltage-mode input encoding, differential current summation, and transimpedance-based readout followed by analog-to-digital conversion, enabling single-cycle signed accumulation without duplicating crossbar resources. A 32 × 16 dual-layer prototype crossbar was fabricated and experimentally characterized. Measurements demonstrate a mean absolute percentage error (MAPE) below 1% within the linear operating region and below 4% over the full-scale conductance range. These results validate the robustness of the proposed mapping methodology and confirm the feasibility of hybrid analog–digital acceleration for edge AI systems. Consequently, this discrete prototype serves as a physical verification platform for the AIMC approach, providing valuable insights for more efficient mixed-signal computing integrated circuit (IC) designs.
(1) Background: In hospitals, mattresses are often relocated for cleaning or patient transfer, leading to mismatches between actual and recorded bed locations. Manual updates are time-consuming and error-prone, requiring an automatic localization system that is cost-effective and easy to deploy to ensure traceability and reduce nursing workload. (2) Purpose: This study presents a pragmatic, large-scale implementation and validation of a BLE-based localization system using RSSI measurements. The goal was to achieve reliable room-level identification of smart mattresses by leveraging existing hospital infrastructure. (3) Results: The system showed stable signals in the complex hospital environment, with a 12.04 dBm mean gap between primary and secondary rooms, accurately detecting mattress movements and restoring location confidence. Nurses reported easier operation, reduced manual checks, and improved accuracy, though occasional mismatches occurred when receivers were offline. (4) Conclusions: The RSSI-based system demonstrates a feasible and scalable model for real-world asset tracking. Future upgrades include receiver health monitoring, watchdog restarts, and enhanced user training to improve reliability and usability. (5) Method: RSSI–distance relationships were characterized under different partition conditions to determine parameters for room differentiation. To evaluate real-world scalability, a field validation involving 266 mattresses in 101 rooms over 42 h tested performance, along with relocation tests and nurse feedback.
In the pursuit of real-time object detection with constrained computational resources, the optimization of neural network architectures is paramount. We introduce novel sparsity induction methods within the YOLOv4-Tiny framework to significantly improve computational efficiency while maintaining high accuracy in pedestrian detection. We present three sparsification approaches: Homogeneous, Progressive, and Layer-Adaptive, each methodically reducing the model’s complexity without compromising its detection capability. Additionally, we refine the model’s output with a memory-efficient sliding window approach and a Bounding Box Sorting Algorithm, ensuring precise Intersection over Union (IoU) calculations. Our results demonstrate a substantial reduction in computational load by zeroing out over 50% of the weights with only a minimal 6% loss in IoU and 0.6% loss in F1-Score.
In the post-Moore’s Law era, conventional Von Neumann architectures face critical limitations, such as the “memory wall” and excessive power consumption, particularly when processing unstructured data. Neuromorphic computing, inspired by the human brain, offers a promising solution through parallel processing and adaptive learning. Among the candidates for artificial synapses, memristors based on two-dimensional MXenes (specifically Ti3C2Tx) have attracted significant attention due to their unique layered structure, high metallic conductivity, and tunable physicochemical properties. This review provides a comprehensive analysis of MXene-based memristors, from material synthesis to system-level applications. We examine how different synthesis strategies, including etching methods, directly influence device performance and elucidate the underlying resistive switching mechanisms driven by ion migration, valence change, and interfacial processes. Furthermore, the review demonstrates the efficacy of MXenes in emulating biological synaptic functions—such as spike-timing-dependent plasticity (STDP) and long-term potentiation/depression (LTP/LTD)—and their application in tasks like handwritten digit recognition. Finally, we highlight emerging frontiers in flexible electronics and in-sensor computing, offering insights into the future trajectory of integrated sensing, memory, and computation.
