This paper demonstrates a 26.5-GHz 2-D Butler matrix based 4×2 array switched beamformer. By using a 2-D Butler matrix, feed lines between IC and antennas are uniform, which is a critical problem in an integrated Butler matrix for a 1- D array since it requires complex phase matched routing on PCB. A proposed switched beamformer consists of a signal distribution IC and two switched beamformer ICs. Reconfigurable switches with a function of power divider/combiner are integrated for additional beam patterns. The proposed switched beamformer can generate total 22 beams, which cover a whole scan angle with a low gain variation. Measured beam patterns show that the proposed switched beamformer can cover any 3-D spatial angle of ±44° in azimuth and ±43° in elevation even with a low spatial beam resolution. To our knowledge, this is the first 2-D array switched beamformer based on the Butler matrix in millimeter wave bands.
In this work we propose a new architecture for a wideband phase shifter, based on upconversion and downconversion of the wideband input signal using phase-shifted mm-wave local oscillator (LO) signals. Phase shifting of the LO at a single frequency is achieved using an on-chip quadrature voltage-controlled oscillator (QVCO) and vector modulation (VM). The issue of mixer image band phase shift interference is mitigated using filtering at the mm-wave intermediate frequency (IF). The concept is demonstrated in 65nm CMOS in the design of a 6–22 GHz full 360° phase shifter using a 84 GHz LO and 62–78 GHz IF range. The phase shifter achieves phase error <1.05° and amplitude error <0.2 dB for 7-bit resolution with power consumption of 137 mW (including buffers) and core area of 0.26 mm 2 .
A 0.324-THz multiplier-based (x16) transmitter with an on-chip patch antenna has been implemented in a 130-nm SiGe:C BiCMOS technology with an $f_{\mathrm{T}}/f_{\mathrm{m}m}$ of 350/450 GHz. Power management and biasing are integrated on-chip for post-silicon optimizations of output power and de-to-THz efficiency. Each circuit block can be programmed over a serial peripheral interface for bias current. Three individually programmable low-dropout voltage regulators supply the x8 20-to-160-GHz multiplier chain, the two-stage 160-GHz power amplifier, and the 0.32-THz frequency doubler, respectively. Measurements after optimization reveal a dc-to-THz efficiency of 2.65% with an output power of 6.6 dBm and a dc power consumption of 170 mW operating at 0.324 THz.
A 140GHz 4-element RF beamforming phased-array receiver (RX) has been demonstrated in 22nm FDSOI CMOS. The proposed single-side-band architecture provides >25dB and >20dB measured image rejection ratio (IRR) across 4GHz and 8GHz channel bandwidth centered at 7GHz intermediate frequency (IF). Each front-end element consists of a wideband low-noise amplifier (LNA) and a vector-modulator phase shifter. The 4 elements are combined on chip through power combiners and driver amplifiers before the double-balanced mixer, which is driven by an on-chip multiplier (x9). The receiver consumes 480mW DC power and provides <10dB noise figure from 135 to 147 GHz. The RX is measured up to 32 and 24Gb/ $s$ in the probe and over-the-air test. To the authors' knowledge, this CMOS RF beamforming RX presents the largest channel bandwidth (8GHz) with 20dB IRRmin at low IF consuming the lowest DC power per element (120mW) among the published phased-array RX in the 140GHz band.
A frequency quadrupler based on cascaded push-push frequency doublers is presented in this work. Push-push frequency doublers suffer from limited power efficiency and conversion gain, mainly due to second-harmonic feedback. Conventional harmonic reflectors minimize this undesired feedback introducing a common-mode second-harmonic resonance, at the price of increased area and reduced bandwidth. In this design the harmonic reflector is embedded into the input matching network, resulting in a more compact design. The coupling coefficient between the multiple windings of the transformer secondary is used to decouple the differential-mode inductance from the common-mode inductance, that acts as a wideband harmonic reflector. A common-gate transistor is stacked with the push-push pair to further boost the output power while reusing the same current. Two push-push frequency doublers are cascaded without additional power amplification stages. The quadrupler, implemented in 28nm CMOS, achieves a peak output power of 0 dBm and peak power efficiency of 50% at 77 GHz and the 3-dB bandwidth is from 70 to 86 GHz.
In this paper, a slotline-based electrical balance duplexer (EBD) with high geometrical symmetry topology and high common mode rejection is proposed to realize high isolation between the transmitter (TX) and receiver (RX). With the proposed EBD structure, a 160-GHz frequency modulated continuous wave (FMCW) radar transceiver with TX/RX antenna sharing architecture is achieved in the 130nm SiGe BiCMOS process. The chirp signal can be generated covering 147 GHz to 165 GHz by adjusting the operating frequency of the push-push voltage-controlled oscillator (VCO) with the external input control voltage. Using spatial power combining slotline-based antennas and a high resistivity silicon lens, the measured effective isotropic radiated power (EIRP) is over 20 dBm. The chip has a die area of 2.21mm(2) and consumes 0.6 W of DC power.
This paper presents a high data rate 140-GHz on-off keying (OOK) CMOS transmitter and receiver chipset implemented in 28nm CMOS process for short-range wireless communications. The transmitter comprises a power amplifier (PA), modulator, CML-to-CMOS converter, and a fundamental voltage-controlled oscillator (VCO). The receiver consists of a low-noise amplifier (LNA), demodulator, and a single-ended to differential converting amplifier. Continuous-time linear equalizers (CTLE) are implemented on transmitter and receiver baseband to extend the baseband bandwidth. The proposed chipset is wire-bonded to an on-board Vivaldi antenna and a FR4 PCB carrier board to reduce the system cost. Despite the low-cost packaging, it demonstrates measured 26-Gb/s and 17-Gb/s error-free (BER<10- 12 ) wireless OOK links at 1 cm and 5 cm distance, respectively. The transmitter and receiver consume 99 mW and 63 mW power consumption, respectively.
A back-off efficient transmit/receive (T/R) front-end module (FEM) architecture is presented in this paper. On one hand, switchless class-G (SLCG) topology is adopted for power amplifier (PA) to improve the back-off efficiency in TX mode. On the other hand, co-design asymmetric T/R switch scheme is applied to reduce the switch loss in TX path. A 4.8-6.4-GHz FEM is implemented in a 0.15-µm GaN-HEMT process for validation, and the chip size is only 1.45 mm ×1.6 mm. The TX mode realizes a saturated power of 37.2-38.9 dBm and a 6-dB back-off drain efficiency (DE) of 40.2%-43.4%. Applying a 160-MHz LTE signal with 8.5-dB PAPR, an average DE of 33.3%-37% at an average power of 28.3-30 dBm is measured, and the ACPR is better than -46 dBc after digital predistortion. The RX mode achieves a noise figure of 1.8-2.2 dB and an IIP3 of 20.8-25 dBm.
This paper presents a new concept of passive phase shifters based on manipulating propagation delay through two parallel transmission lines periodically connected via digitally controlled switch networks. The proposed approach enables precise phase control and flat amplitude response across different phase settings. The prototype IC is fabricated in a 45 nm RFSOI process and occupies only 0.033 mm 2 . The phase control operates with 11.25°steps over 360° at 140 GHz while maintaining an RMS phase error of 1.2°. The insertion loss is 11.5 dB with < ±0.8 dB variation. Among published D-band phase shifters, this work achieves the lowest RMS phase error and reports bi-directional phase control over 360° and calibration-free operation.
This paper presents a 4-path series-parallel combined highly-efficient class-AB power amplifier (PA) with broad bandwidth and low AM-PM distortion in CMOS process. Frequency staggered tuning scheme enables a wide passband of 23-30GHz. AM-PM distortion is minimized by utilizing PMOS varactors that mitigate the voltage dependence of transistor intrinsic capacitors and harmonic traps that minimize common-mode voltage swings at the second-harmonic frequency. Complete electromagnetic modeling ensures the proposed PA achieve its full potential. Fabricated in a 40nm CMOS process, the PA achieves 38.5% peak power added efficiency (PAE), 23.0dBm saturated output power (P sat ) and 20.4dBm output 1-dB compression point (P 1dB ) with 29.5% PAE. The peak PAE is above 35% and P sat /P ldB remains above 21.5dBm/19.5dBm across 23-30GHz respectively. The minimum normalized AM-PM distortion is less than 1.3°at 26 GHz and remains less than 4.4°across 26-30GHz. Measured EVM/ACLR is below -29dB/-29dBc with 64QAM 5G-NR modulated signal at 28GHz.
Dr. Younkin will share his vision for the future of global semiconductor technologies and design, especially those that will enable future RFIC breakthroughs. Dr. Younkin will discuss the status of government investments and opportunities arising from the CHIPS and SCIENCE ACT of 2022, Korea's K-Belt strategy, Europe's CHIPS ACT, and more. Dr. Younkin leads a global research agenda of about $100M annually, supported by ~3k academic and industrial researchers, 27 international companies, and 3 U.S. government agencies (DARPA, NSF, and NIST). They have defined the opportunities for future compute and communication systems, as outlined by SRC's 2030 Decadal Plan for Semiconductors, and are now working with over 90 organizations to define the semiconductor hardware opportunities that will deliver that required system performance, via the NIST Microelectronic and Advanced Packaging Technologies (MAPT) Roadmap, awarded in April 2022 and scheduled for completion by September 2023.
This paper presents an efficient 0.4 THz single-element radiator implemented in 90nm SiGe BiCMOS. It consists of a PIN diode quadrupler, where a mm-wave Colpitts oscillator at 100 GHz drives a PIN diode switching-reactance-multiplier into reverse recovery. Because of this, the PIN diode abruptly switches between two impedance states and produces strong harmonics. Harmonic injection locking is also presented in this work, where two quadrupler cells are mutually interlocked, and their fourth harmonic power at 0.4 THz combines at the antenna. The radiator achieves a peak EIRP of +20.6 dBm and -5.8 dBm radiated power at 398 GHz, with a 10.7 % tuning range, and consumes 130 mW DC power. This work has a DC-to-THz generation efficiency of 0.2%, the highest reported efficiency above 320 GHz, and achieves the highest power and EIRP generated by a single-element radiator.
A dual-band, concurrent 2.4G wireless local-area network (WLAN) and 2.4G narrow band (NB) transmitter (TX) with on-chip feedforward TX-to-TX interference cancellation path for low antenna-to-antenna isolation in internet of things (IoT) devices is proposed. The on-chip cancellation path generates a replica signal of the same magnitude but 180 $<^>{\circ}$ out-of-phase with respect to the "aggressor" TX signal appearing at the "victim" TX output. An on-chip third-order intermodulation distortion (IMD3) calibration engine carries out the cancellation calibration across all channel combinations in NB and WLAN using an over-the-air antenna-to-antenna channel, and the measured IMD3 product is reduced by 25 dB. Additionally, the maximum output power during concurrent transmission, while meeting the FCC out-of-band emission specification, improves from 10 to 17 dBm across all WLAN channels in a certified FCC out-of-band emission test. With this proposed architecture, the issue of TX-to-TX interference in multiradio coexistence is finally addressed, opening the door to future high-power concurrent multiband TXs in reconfigurable IoT devices.
Digital beam-forming requires highly linear receivers (RXs), as null steering is performed only in digital baseband (BB). This paper presents a highly linear RX, with a high out-of-band (OOB) blocker tolerance without sacrificing performance or power, utilizing a highly linear inverter low-noise amplifier (LNA), followed by an N-path mixer with tunable filtering properties and a BB transimpedance (TIA) amplifier for linearity enhancement. The N-path mixer design trade-offs are discussed, and several linear LNA topologies are presented and compared. A chip prototype was manufactured in a TSMC 65 nm CMOS process. In our implementation, a <4 dB noise figure (NF) is achieved, with an RX gain of 40 dB, in-band (IB) IIP3 of -20 dBm and -3.5 dBm BldB at a 500 MHz offset, while occupying an active area of 1.62 mm 2 and drawing a total power of 76.8 mW. at a frequency range of 22–31 GHz.
This paper presents a broadband optical receiver that employs multiple bandwidth extension techniques in the analog front-end (AFE) and has efficient digital clock and data recovery (CDR). Total AFE bandwidth is extended by 5.5X with continuous-time linear-equalizer (CTLE) peaking, series inductances between each AFE stage, and active inductors in the CTLE output and variable gain amplifier (VGA) stages. The resolution of a digitally controlled oscillator (DCO) is optimized at 9-bit to balance quantization and random noise-induced jitter from the CDR. Fabricated in 28nm CMOS, the 42.7Gb/s optical receiver achieves an optical modulation amplitude (OMA) sensitivity of -3.6dBm at a bit error rate (BER)-12 , 10MHz CDR bandwidth, and 3.4pJ/bit energy efficiency.
We describe the application of Artificial Neural Networks (ANNs) for Gallium Nitride (GaN) High-Electron Mobility Transistor (HEMT) model parameter extraction to improve the model accuracy between 110 and 170 GHz. Fully-connected ANNs trained by backpropagation relate the physics-based ASM-HEMT model parameters to RF transistor measurements. The effects of ANN activation function, number of layers, number of nodes and number of training set data points on training accuracy are studied. For the 12 model parameters that dominate the 40-nm GaN HEMT RF characterization, we obtained a combined root-mean-squared (RMS) error of 2.5% between the ANN prediction and the training set, which is acceptable for most design tasks.
This paper presents a baseband to D-band wireless link based on a transmitter module integrating a 45-nm CMOS channel bonding chipset and a high-gain antenna in PCB technology. The link realized using a commercial receiver at 42 cm achieves a data rate of 57.6 Gb/s using a multi-channel 16-QAM with a transmitting energy efficiency of 27.4 pJ/b.
This work presents a compact double-balanced frequency doubler achieving better than 70% drain and 25% total power efficiency. Complementary NMOS and PMOS devices enable a truly double-balanced frequency doubler. This work's complementary current reuse structure implements voltage scaling in the device. Voltage scaling enables each device to operate at half the effective supply voltage improving efficiency. The stacked design with inverted NMOS and PMOS positions allows deep class C biasing for an effective VGS of negative 0.5V without on-chip negative voltage generation. These techniques enable a high-efficiency frequency doubler, showing nearly 3x higher drain efficiency and 25% higher total efficiency than previously published frequency doublers. This device offers almost 60% higher efficiency than devices without active second harmonic gain. This work also shows wide-band operation with over 23GHz RF BW and excellent output power of 9.8dBm. Implemented in a commercial 45nm SOI technology, this device presents one of the smallest area consumptions in the literature thanks to the complementary current reuse implementation.
The extended manual layout process for RF and analog/mixed-signal design restricts design space exploration and limits design productivity. This work demonstrates the efficacy of an automated layout generator versus a manual approach using a state-of-the-art MIMO receiver. Multiple smaller floorplans of the layout are generated automatically in hours compared to weeks for a single manual layout. Measured results from an automatically generated layout fabricated in TSMC 65nm CMOS show performance numbers comparable to the manual design. Measured in-band/in-notch IIP 3 and out-of-band/in-notch IIP 3 are 18.3dBm and 23.64dBm, respectively.
This paper presents a Wi-Fi RF transceiver with a 2.4GHz/5GHz/6GHz tri-band switchable design. To support the wide 320MHz channel BW for Wi-Fi 7, the RF LC-tank response and TXLPF drooping are compensated via a proposed TX flatness calibration scheme that flattens the amplitude difference over the 320MHz signal bandwidth and improves the EVM over each sub-carrier. This work also proposes a reset-pulse XO design to significantly reduce the XO phase noise. A VCO pushing compensation and calibration technique is developed to suppress the sensitivity to LDO noise and DC-DC spurs. The integrated PLL RMS jitter is 57.9fs at 7.115GHz. The measured TX EVM floor achieves -42.6dB at OdBm output power with EHT320 4096-QAM signals. This RF Transceiver occupies 3.74mm 2 in 55nm CMOS technology.
