This paper analyzes techniques of estimating solutions for the transcendental thermionic emission equation, used in characterizing forward electrical behavior of high-temperature-capable Schottky diodes. Two optimization procedures are investigated: the Newton-Raphson approach and Halley’s method. Equation manipulations are presented for both techniques, which facilitate convergence and avoid numerical overflows. Suitable parameter initialization, ease of implementation and convergence speed are also discussed. Both methods give fully compatible current-voltage estimations, which are also relevant for experimental measurements, as obtained on practical SiC-Schottky diodes.
Identifying defect patterns in a wafer map during manufacturing is crucial to find the root cause of the underlying issue and provides valuable insights on improving yield in the foundry. Currently used methods use deep neural networks(DNN’s) to identify the defects. These DNN’s are generally very huge and have significant inference time. They also require GPU support to efficiently operate. All these issues make these models not fit for on-line prediction in the manufacturing foundry. In this paper, we propose an extremely simple yet effective technique to extract features from wafer images. The proposed method is extremely fast, intuitive, and non-parametric while being explainable. The experiment results show that the proposed pipeline outperforms conventional deep learning models on the tested dataset. Our feature extraction requires no training or fine-tuning while preserving the relative shape and location of data points as revealed by our interpretability analysis.
This paper presents a simple testing methodology for chemosensitive RH sensors, which was applied to study the response of a conductive polymer Poly3,4-EthyleneDiOxyThiophene: Polystyrene Sulfonate (PEDOT: PSS) mixed with different binders: Polyvinylpyrrolidone (PVP), Polyethylene Glycol (PEG) and Ethyl Cellulose (EC) at 11 RH levels in a cycling manner (hysteresis). These binders enhanced the adhesion of the RH-sensitive material to the substrate and contributed to characteristic linearisation and more negligible hysteresis. As a test vehicle, we used an Inter Digital Transducer (IDT) made of Polyimide (PI), having a finger/space dimension equal to 25 micro-meter and a sensitive area of 4mm x 4mm. IDTs were fabricated by photolithography on Cr/Au metalized PI substrate (in vacuum by EB). The enhanced electrical characteristics of sensors obtained by mixing PEDOT: PSS with binders were analyzed and discussed in detail.
This study aims to analyze and compare the characteristics of Metal-Insulator-Metal (MIM) capacitors, focusing on the effect of the stacking selection of thick dielectric materials, for future applications requiring robustness to high voltages and temperatures. The 300 nm-thick dielectric stacks under investigation include SiO 2 and Si 3 N 4 materials deposited using plasma-enhanced chemical vapor deposition (PECVD) at a high temperature (300°C), as well as Al 2 O 3 deposited through reactive sputtering at room temperature. The experimental results presented in this work highlight the importance of the stacking choice of these dielectric materials for minimizing the residual stress and the temperature coefficient of capacitance (TCC) and enhancing the overall dielectric constant. These factors contribute to achieving increased capacitance density, with mechanical and electrical resistance to harsh conditions.
This article presents an approach for implementing a Cylindrical Nanowire Single Channel Field Effect Transistor (SCFET) without the use of doping in the channel region (dopingless). Using an appropriate work function for the outer metal electrode and the Charge Plasma (CP) process, the n-type semiconductor is produced, where a single channel is used. By placing the gate length (LG) at 1$\theta$ nm, with channel and oxide thicknesses of 5 and 1 nm each, Sentaurus Technology Computer-Aided Design (TCAD) simulations are employed to compare the electrical properties of the proposed device to a normally undoped double gate MOSFET. Instead of two channels with identical spacing among vertical stackings, the NWSCFET has a single narrow channel. Utilising the linked Drift-Diffusion (DD) technique and Shockley-Read-Hall Recombination (SRH) method, the device performance has been quantitatively assessed. In accordance with the charge plasma and single-channel approach, the current obtained for the single-channel device has almost been doubled when compared with a Cylindrical Gate-All-Around double-channel NW MOSFET. In addition to the above parameters, the Short Channel Effects (SCE) have been reduced up to a certain extent.
Nanostructured silicon substrate has been intensively studied in the last years, as promising platform for Surface-enhanced Raman scattering applications. Si based conical shape nanostructures - Si nanotrees, decorated with small Ag nanocubes, are used to improve the Raman signal for molecules detection (e.g. organic dyes). Here in, substrates with a discontinuous film of Ag, deposited on the nanostructured silicon, are fabricated in order to improve the Raman signal even more. Morphological properties are analyzed by using SEM images. Absorbance properties of the fabricated nanocubes are also investigated. Crystal violet was chosen to evaluate the performances of our fabricated detection platform. A good value of $1.5\times 10^{8}$ for enhancement factor, in the case of modified silicon nanotrees like substrate, is determined.
In this paper we are assessing the memristive properties of heterojunctions based on Reduced Graphene Oxide:PVA nanocomposite - interdigitated comb structure Al / Au on Glass substrate. By using simple micro-fabrication technological steps we have obtained an interdigitated comb on glass substrate. Al and Au electrodes were patterned through lift-off. We used 2 ratios for RGO:PVA nanocomposite: one with 0 PVA and the other one’s ratio RGO:PVA is 3:1. These solutions were deposited, left to dry and thermally annealed. Raman Spectroscopy was used to investigate the resulting samples. I-V characteristics corresponding to the sample having 0 PVA have hysteresis, which confirms a memristive response.
Modelling the integrated circuits performance dependencies on design parameters using machine learning regressions is becoming widely used in various applications like circuit design and optimization or verification. For constructing such models, a certain amount of input-output sample pairs needs to be acquired through circuit simulations. Depending on the circuit complexity this process can become very costly in what regards both time and licensing expenses. In this paper, we propose a sampling scheme for minimizing the number of samples needed to create accurate and reliable regression models by using an active learning approach. We explore the possibility of achieving this using Gaussian Process regression within an active learning scheme based on the particular regression model uncertainty. We validate the concept on synthetic functions used as a placeholder for circuit behavior and also for a simulated LDO circuit.
In the last decades, lots of research have been performed with the purpose of obtaining solar cells with improved properties, and for extending their use in energy harvesting (EH) applications. In this paper, we designed and simulated two different solar cells, one based on organic materials and the other on amorphous silicon (a-Si), each in two different light intensity conditions (corresponding to outdoor and indoor functioning, respectively). We compared their performance in terms of the main characteristics and parameters and concluded that the organic solar cells have better results than the a-Si ones and have promising perspectives for being used in EH applications, in low light or indoor situations. As compared to other literature research, our paper proposes a careful choice of materials and parameters, for the PEDOT:PSS-based organic solar cell, to improve its performance; moreover, the use of the AFORS-HET software enabled us to perform a detailed comparative analysis of two different structures of solar cells, at two different illumination levels (to estimate the behaviour both in outdoor and indoor conditions), that could be followed by an experimental validation and testing of a real structure.
An integrated Digital Temperature Sensor with a High Speed I 2 C interface (HS I 2 C DTS) is designed, simulated and SI implemented in a 0.18μm EEPROM CMOS process. The system operates for power supply voltages from 1.6V to 3.6V and temperatures from -40°C to 125°C. The simulation results of HS I 2 C DTS with a proposed digital output buffer with open drain output stage exhibit a maximum data hold time of 60ns, being twice as fast as the system with the standard topology of the output buffer. Two encapsulated HS I 2 C DTS were measured in the same conditions. The experimental results of the data hold time for the entire system are between 61.13…85.74ns.
One of the main degradation mechanisms of methy-lammonium lead iodine (MAPI), which is an important material for perovskite based solar cells, is the migration of iodide ions. It is believed that this phenomenon is in fact dominated by the diffusion of iodide vacancies. In this paper, we suggest that the addition of a small amount of $\mathrm{O}\mathrm{H}^{-}$ ions can help suppress the migration of iodide and increase the overall stability of the material. Through the use of molecular dynamics simulations, we show that the $\mathrm{O}\mathrm{H}^{-}$ ions can bind to the positively charged iodide vacancies and can block the access of the negative iodide ions into those vacancies.
$NO_{2}$ emissions are one of the main sources of pollution in urban environments. Thus, gas sensors based on gold interdigitated electrodes and polypyrrole sensing layers have been investigated for its monitoring at room temperature. During the investigation it was determined that the addition of Ferrocene to a sensing layer consisting of a polypyrrole, reduced graphene oxide composite material sensing layer leads to a significant increase in both the sensitivity and linearity of the resulting sensor. Moreover, polypyrrole sensors have been identified to have excellent temporal stability, retaining a reproducible measurement even after two years of storage.
We present the manufacturing of a microfluidic-electrochemical biosensor with interdigitated electrodes. We performed electrical tests for three different samples containing acetylcholinesterase, anti-CD3 and CD3 to identify the protein concentration. We established that the current is measured in relation to the reaction time at a fixed potential, which allows the detection of protein concentration at 4 mM and 10 mM. In particular the methods of using these proteins and compounds, preferably antibodies, which bind or modulate the activities of these proteins, are used to treat cancer, allergies, infections and inflammatory conditions. Electrochemical biosensors have become victorious candidates for medical development due to the ease of turning a biological interaction into an electrical signal. The aim of this work is to use the biosensor to detect the concentration of proteins and antigens that have anti-inflammatory action. Electrical tests show that the current increases with increasing protein concentration. The electrical tests were performed by KEITHLEY current-voltage and time analyser.
This paper presents two techniques to improve overall performance of transconductors. These techniques are easy to implement with little additional power and area consumption, but they offer significant improvements over standard structures. The structures have been implemented in a 130nm CMOS process for automotive applications and used in a low dropout (LDO) regulator. To ensure the LDO’s stability over a wide range of conditions, a 3rd order RC ladder compensation network is studied, and a sizing strategy based on simulations is proposed. Significant enhancements have been made in terms of transient performance, primarily through improvements in output dynamic current capability. The OTAs’ slew rate was up to 50 times larger, while also having the gain bandwidth (GBW) improved by a factor of 8. This transposes into better load transient response performance for the LDO by an average of 50%.
This paper presents a comprehensive TCAD (Technology Computer-Aided Design) modelling study focused on multi-channel Gallium Nitride (GaN) devices, with a particular emphasis on tri-gate structures. Recently GaN based devices have gained considerable momentum in the power electronics applications. Multi-channel devices utilize AlGaN/GaN heterostructures placed on top of each other to provide parallel conduction paths formed of individual two-dimensional-electron-gas (2DEG) layers. Such devices have considerably lower on-state resistance when compared to conventional GaN devices. Specifically, a 5-channel structure can achieve a net 2DEG density of $2.5\times 10^{13}cm^{-2}$. TCAD simulations provide valuable insights into device behavior, allowing for optimization of performance and design parameters. To achieve normally-off operation a tri-gate structure is employed in the third dimension. Given the challenging architecture of this device, complex 3D simulations are employed, and the outcomes are reported in this paper.
This paper presents the sizing strategies of the main protection mechanisms used in nowadays widely spread power management ICs that incorporate linear regulators. An OverVoltage, UnderVoltage and a Thermal Shutdown protection circuit are presented with details on the design specifications and simulation results obtained that confirm their correct functionalities. The protection circuits were designed in a 180nm CMOS technology, the main parameters being verified over PVT and extreme conditions.
Manual circuit sizing is an iterative process that negatively impacts the productivity and work satisfaction of experienced analog circuit designers. Thus, many automated circuit sizing methods have been proposed recently. However, they have poor performances on highly unstable circuits for which most of the simulations fail to converge. We propose a simple, yet powerful technique that can be used in conjunction with the state-of-the-art optimization algorithms for circuit sizing. This technique is inspired by the analog designers' way of working. First, the algorithm finds the stability region by optimizing for the nominal corner, then it takes the other operating corners into consideration for the rest of the optimization process. We test our sizing method on a multiloop LDO for which the classical automated sizing methods cannot find circuit configurations that meet the specifications.
In a monolithically integrated GaN-IC, the parasitic inductance, capacitance and resistance between the driver and the half-bridge is greatly reduced. In a GaN-IC platform on SOI combined with oxide filled deep trench isolation, the back-gating effect on the high-side power device is eliminated. Yet some issues related to the epitaxial stack and the substrate contact layer need to be addressed. In this paper, a substrate network concept is presented for 200V p-GaN gate HEMTs on SOI, and the impact of the epitaxial stack on device operation is investigated through modeling the epitaxial stack as a parallel R-C network. Double pulse tests were simulated and the impact on the substrate current was investigated. It is concluded that the substrate current peaks have a strong dependency on the epitaxial stack and the switching times, and that the peaks can be reduced by increasing the substrate layer resistivity.
We preset the results of the study on thermoelectric properties and oscillatory effects layers and foils) based on p-type Bi 2 Te 3 topological insulators and n-type Bi 0.84 Sb 0.16 foils $(d=10-20\mu\mathrm{m})$. Analysis of the Shubnikov-de Haas oscillations of p-type Bi2 Te 3 single-crystal layers has confirmed the presence of surface states in layers with a high quantum charge carrier mobility of up to $20\times 10^{3} \mathrm{cm}^{2}/(\mathrm{Vs})$ and a Fermi surface anisotropy of $A=4$, which are characteristic of bulk topological insulator. It has been revealed that the thermal conductivity of the foils in a temperature range of 300-100 K remains constant. Based on a technology developed by the authors for forming unsupported p-type Bi 2 Te 3 single-crystal micro-layers and an n-type Bi 0.84 Sb 0.16 foils a device was constructed that provides a temperature gradient of $\Delta T=9\mathrm{~K}$ over an area of $0.01\mathrm{~cm}^{2}$. Structures based on Bi 2 Te 3 can be used to design miniature sensors for thermoelectric devices, such as thermoelectric coolers, in particular, for cooling a computer processor.
Brushless DC (BLDC) electric motors are used worldwide for their efficiency, controllability, reduced power operability, high durability, and low noise. Replicating the real application set up in the simulation world, BLDC motors can be implemented in modern Spice programs in order to improve verification and testing processes. This paper presents an original behavioral modeling method to control three MOSFET half bridges used to drive a BLDC motor load based on feedback loop provided by the motor shaft angle. The PSpice motor load is implemented using real BLDC motor parameters, shaft angle and shaft speed being the reference motor parameters in order to monitor if a complete rotation is performed. The simulation results are compared with the real measurements and demonstrate the proof of the behavioral modeling concept on this specific automotive application.
