We extend Cyclic Redundancy Checks (CRCs) beyond error detection by enabling threshold-guided error correction with the SOGRAND chip. Traditionally, CRCs treat any codeword that passes the CRC check as valid, and request retransmission whenever the check fails. GRAND-family decoders use a noise-guessing approach to recover packets that fail the CRC check; however, undetected errors can occur when an incorrect codeword satisfies the CRC check, resulting in a penalty in the undetected error rate. SOGRAND decodes CRCs and computes soft-outputs to derive an accurate a posteriori probability for each decoded result. Applying a threshold on the a posteriori probabilities enables control over retransmission requests and the undetected error rate. Fabricated in 40nm CMOS, SOGRAND achieves 0.84pJ/bit energy and 11.3ns latency, outperforming the state-of-the-art decoders while enabling confidence-aware CRC error correction through accurate soft-output computation.
To meet the rising demand for multi-Gb/s wireless communications in dynamic scenarios, mm-Wave transceivers featuring large output power, high-accuracy beam directivity and wide gain range are essential [1]–[10]. According to the 5G NR and IEEE 802.11ad/ay standards, the phased-array transceivers usually operate in the time-division duplex (TDD) mode by sharing the antenna for both the transmitter (TX) and receiver (RX). However, the large insertion loss and narrow bandwidth of the conventional bulky $\lambda / 4 \mathrm{T} / \mathrm{R}$ switch significantly limit the transceiver performance [1]. To reduce loss and save area, the transformer-based T/R switches have been leveraged, but they always encounter reduced TX-RX isolation and increased TRX co-design difficulties around 60 GHz [2]–[4]. Besides, for precise beam steering and low sidelobes, high-accuracy gain and phase controllers with large range are crucial. Unfortunately, for 60 GHz transceivers, their gain ranges are typically limited to $<20 \text{dB}$ with around $0.4 \text{dB} / 5^{\circ}$ gain/phase errors [2]–[4].
Training today's complex AI models, such as transformers, requires the use of distributed compute platforms within data centers involving coordinated execution across thousands of GPUs [1]. The connectivity between these compute sockets needs to support high data rates, incur low latency, and be energy efficient to ensure that the time-to-accuracy during training is minimized. Forward error correction (FEC) is a critical enabler of data center connectivity due to its ability to relax the SNR requirements on the analog front-end, thereby enabling signaling rates in the 100s of GBaud. However, the impact and role of FEC to support a high-performance distributed compute fabric is not well understood. This paper makes three contributions: 1) it derives specifications on FEC for connectivity; 2) it hypothesizes that binary BCH codes are an excellent baseline FEC for connectivity; and 3) it validates this hypothesis via the design of a BCH(255, 207) decoder in 16nm FinFET.
Global Positioning System (GPS)-based localization services play a critical role in industrial, agricultural, and wearable applications. To acquire its location (Acquisition), a GPS receiver (Rx) performs intensive processing on signals transmitted by orbiting satellites. This processing dominates energy consumption, restricting broader adoption of GPS technology in energy-constrained applications. This paper presents a correlator that uses Adaptive Compressive Sampling (CS) to significantly reduce the energy consumption in GPS Rx by reducing the number of operations (opCount) involved in Acquisition.
Integrated circuit chips, such as controllers for superconducting quantum computing and readout circuits for infrared astronomical detectors, need to operate in the cryogenic temperature region of liquid nitrogen and even in the deep cryogenic temperature region of liquid helium. However, as shown in Fig. 1 (top left), as the number of transistors increases, the power consumption of the chip increases and some overheated areas in the chip may cause it to fail. Therefore, there is a strong requirement for on-chip deep cryogenic CMOS temperature sensors for temperature monitoring. In Fig. 1 (bottom), CMOS temperature sensors are mainly categorized as BJT-based, resistor-based, and MOS-based. Unfortunately, in BJT-based sensors, the CTAT characteristics of VBE and the PTAT characteristics of $\Delta \mathrm{V}_{\text{BE}}$ lose linearity below approximately 60K [1]. In resistor-based sensors, the NWELL resistors exhibit high non-linearity in the whole temperature range while the unsilicided P-Poly resistors and other kinds of resistors perform resistance saturation below approximately 60K [2]. In MOS-based sensors, the threshold voltage of NMOS transistors exhibits saturation below approximately 50K [2]–[4]. Therefore, none of the above sensors can be used for temperature sensing at deep cryogenic temperatures. Fig. 1 (top right) shows the different characteristics of PMOS threshold voltage in different temperature ranges. Above the critical temperature $\mathrm{T}_{\mathrm{C}}$, the threshold voltage of the PMOS transistor shows a linear temperature dependence due to Fermi potential based on the theory of semiconductor device physics. Below $\mathrm{T}_{\mathrm{C}}$, as the temperature decreases, some experimental results have observed that the PMOS threshold voltage presents higher temperature sensitivity at deep cryogenic temperatures [3], [4]. Currently, the mechanism behind this phenomenon has not been clearly explained. One study models this phenomenon to the change in $\mathrm{C}_{0\mathrm{X}}$ with temperature, and proposes a temperature function of $\mathrm{C}_{0\mathrm{X}}$ that agrees with the experimental results [3]. Another study interprets that as the temperature decreases, the interface-trap charge density near the band edge follows an exponential increase, leading to the higher temperature sensitivity [4]. The sensitive relationship between threshold voltage and temperature is related to the process. Some results indicate that threshold voltage in advanced processes is not suitable for temperature sensing [4]. However, according to our experimental data, the threshold voltage in 0.18um and 0.13um processes exhibits excellent temperature sensing characteristics. Considering the good linearity of PMOS transistors using 0.13um process in the high-temperature region and the high sensitivity in the low-temperature region, in this paper, we design a deep cryogenic CMOS temperature sensor based on a PMOS transistor, with an operating range from 10K (-263°C) to 410K (137°C) and a relative inaccuracy of 0.5%) (3σ).
Buck converters using zero-voltage switching (ZVS) techniques are widely used to reduce the significant turn-on V-I overlap loss associated with high-voltage (HV) power switches. The primary challenge in ZVS techniques lies in constructing an efficient current path to charge the switching node with minimal additional components and extra loss. Approaches like using negative inductor current from the buck topology [1]–[2] or adding a small resonant branch parallel to it [3] can achieve ZVS, but they lead to large inductor current ripples or continuous resonant inductor current, causing significant conduction losses under heavy loads. To address these losses, various approaches utilizing auxiliary discontinuous inductor currents have been proposed [4]–[8]. In [4]–[5], auxiliary inductors energized by VOUT and $2/3 V_{\text{OUT}}$ gradually introduce current into the main path until it exceeds the load current $(\mathrm{I}_{0})$ and charges the switching node, leading to significant losses at low output voltages and heavy loads. An auxiliary inductor energized by VIN $(\mathrm{V}_{1\mathrm{N}_{-}\text{MAX}}=20\mathrm{V}$ in [6] enables faster charging but creates reliability concerns due to high di/dt current pulses at higher input voltages, requiring large $\mu \mathrm{H}$ -level inductors solely for ZVS, which is inefficient. To balance reliability and cost, reducing the voltage across the auxiliary inductor allows the use of a smaller inductor for ZVS without reliability issues. This is shown in [7]–[8], where an auxiliary capacitor energizes a 30nH auxiliary inductor [8]. However, it remains uncertain whether the conduction loss introduced by the ZVS branch is fully optimized. On the other hand, the limited slew rate of the main inductor current $(\mathrm{I}_{\mathrm{L}})$ continues to pose a challenge in improving the load transient response of hundred-kHz ZVS buck converters, while using an auxiliary inductor solely for ZVS operation seems inefficient and wasteful.
Biomedical signal processing systems-on-chip (SoC) have shown significant promise in human-machine interfaces and closed-loop neuromodulation applications [1]–[5]. Future personalized medical wearables are anticipated to provide long-term monitoring and accurate interpretation while maintaining minimal energy consumption [6]–[8]. Lightweight neural networks, such as binary, spiking, and convolutional neural networks (BNN/SNN/CNN), are promising for neural signal analysis, with neural architecture search (NAS) techniques enabling the deployment of task-specific models optimized for accuracy and efficiency [9]–[12]. However, developing an accurate, ultra-energy-efficient medical SoC that seamlessly integrates signal feature extraction and processing with multi-model reconfigurability remains challenging. Furthermore, inter-patient variance adversely affects the accuracy of biosignal classifications in real-world scenarios, thereby limiting the reliability of these devices [13], [14].
The abundant spectrum resource and short wavelength of THz electromagnetic waves make these bands attractive for B5G and 6G wireless communications. In 2017, the frequency band from 252 to 322GHz (called “300-GHz-band” hereafter) was allocated for high-speed point-to-point (P2P) links in the standard IEEE std. 802.15.3d [1]. A broadband THz receiver is essential in such applications to fully utilize the rich spectrum of THz bands. However, it is challenging to design a broadband THz receiver operating beyond the $f_{\max}$ of CMOS processes because transistors can not provide any power gain, and passive components are lossy in these bands. Previous works have made numerous efforts to demonstrate 300-GHz-band CMOS receivers [2]–[9], but a broadband CMOS receiver covering the whole IEEE std. 802.15.3d band has yet to be reported so far. One solution to these challenges is proposed in this work; namely, a 228-324GHz RF domain quadrature receiver utilizing a broadband LO generator with a 4.27dBm peak output power in a 65nm bulk CMOS technology with an fmapt of 250GHz.
High voltage DC-DC boost converters are essential for a variety of applications, including LED backlighting [1], piezoelectric actuators [2], the bias of optoelectronic devices in LiDAR systems [3], and so on. Given that the input voltage is relatively low when powered by a lithium-ion (Li-ion) battery, achieving a high conversion ratio (CR) is crucial. A conventional boost topology is illustrated in Fig. 1 (top). To realize high CR and output voltage, several challenges arise: 1) The limited CR of conventional boost brings a large duty ratio $D$, which not only restricts the switching frequency $(\mathrm{F}_{\text{SW}})$ due to the minimum on-time of power switches, but also leads to a significant inductor current ripple. 2) The power switches and inductor suffer from high voltage stress due to the elevated output voltage, necessitating the use of high-voltage LDMOS and inductors. This, in turn, results in larger on-resistance, ultimately reducing power conversion efficiency. 3) As the CR increases, the ratio between the inductor current $l_{\mathrm{L}}$ and the output current $l_{\text{OUT}}$ rises, resulting in a higher average inductor current in high CR converters than those with lower CR.
STT-MRAM emerges as one of the promising candidates for next-generation non-volatile memory, offering versatility across diverse applications [1]–[6]. However, designing high-reliability MRAM for automotive and aerospace applications is particularly challenging. It demands operation across wide temperature ranges while balancing retention, write speed, and endurance in extreme environments [7]. It remains a great challenge for wide-temperature design of reliable STT-MRAM operating from -55°C to 125°C with high wafer-level die yield: (1) Operations in MRAM chip necessitate multiple input voltages that are sensitive to temperature and process variations. Despite this critical requirement, a thorough analysis of on-chip power delivery architectures has been largely overlooked in prior MRAM designs. (2) Wide-temperature MRAM encounters breakdown and endurance degradation at low temperature, significantly affecting its reliability and suitability in extreme environments [8]. (3) Traditional MRAM yield analysis, primarily based on single-device tests or MT J arrays, inadequately considers die-to-die variations, circuit-system interactions, and real-world operating conditions, leading to statistically insignificant results.
Voltage references provide a critical function to nearly any System-on-Chip (SoC) and will remain indispensable in future process nodes. New challenges arise from aggressive scaling, for example the degrading linearity of bipolar devices in FinFET CMOS [1]. While the classic bandgap reference may often provide a robust performance [2], it cannot serve the reduced supply headroom in modern technologies. Several alternative solutions were developed which can work in a Sub-1V domain, like in [3]–[5]. However, the pn-junction voltage at cold temperatures (- 0.8V) presents a physical limit for operation at very low supply. Hence, the decreasing (digital) core voltages of VDD $\leq 0.8\mathrm{V}$ motivate a MOS-based reference, like in this paper.
The growth of data-intensive applications such as large language AI models has increased the demand for higher data throughput in wireline links. Due to the bandwidth-limited nature of the wireline channel, increasing the data rates across the same physical distance of the communication channel results in more inter-symbol interference (ISI). Consequently, more channel equalization is required to compensate for ISI, which increases the energy/bit of the communication link. Researchers have discovered that machine learning (ML) inspired approaches [1]–[2] including feature extraction and classification provide a more efficient solution for compensating the channel loss compared to the conventional equalization techniques like FFE, DFE, and CTLEs [3]–[7]. However, the prior works on ML inspired links are limited to NRZ modulation only. In this work, we introduce an energy-efficient ML inspired transceiver that leverages feature extraction and classification to transmit encoded PAM-4 data across a wide range of channel loss (13dB to 26dB) while maintaining BER < 10−11 without using any conventional equalizers. Additionally, we propose a data encoding scheme, consecutive symbol to center encoding (CSC) to encode PAM-4 and provide identifiable attributes to the transmitted signal, which helps to increase the channel loss compensation range and reduce the complexity of the classifier. Since ISI is a deterministic non-ideality, the proposed decision-tree based classifier (on-chip) is designed to learn both the channel characteristics and the CSC data encoding, enabling it to accurately detect the original transmitted data in the presence of ISI with a latency of only 10 unit interval (UI). The decision tree classifier operates with a low-power feed-forward architecture without any feedback timing constraints, allowing the proposed transceiver to achieve 0.055pJ/bit/dB, which is ~2x lower than prior work [3]–[5] while compensating for nearly the same channel loss.
The growing demands of cryogenic quantum computing and wide-bandwidth aerospace/automotive wireless communications have created a demand for ADC technologies capable of operating across unprecedented temperature ranges, from room temperature down to 4K, while achieving higher sampling rates and resolution. While pipelined ADC architectures offer a promising solution, their residue amplifier designs face significant challenges in wide-temperature operation, whether implemented as multi-stage closed-loop amplifiers or open-loop amplifiers (Fig. 1). The fundamental challenge lies in the dramatic device parameter variations at cryogenic temperatures, where threshold voltage (Vt) shifts by approximately 100mV and carrier mobility increases by more than 1.5x [1]. These variations create distinct limitations for existing architectures. Multi-stage closed-loop amplifiers require complex bias calibration to maintain stability [2], while open-loop amplifiers [3]–[5] suffer from large gain variations [4], necessitating an unacceptable redundancy range. Open-loop amplifiers also suffer poor linearity, which mandates a high-resolution 1 st stage SAR quantizer and leads to longer conversion times [5].
High performance multi-core CPUs and GPUs in data centers demand high current (>100A) and exhibit rapid load transients (>1000A/µs), posing significant challenges for existing 48V-to-1V converters, which often struggle to balance efficiency and transient response [1]–[4]. For example, hybrid converters [1] [2], which utilize switched capacitors to reduce voltage stress on power transistors, demonstrate improved peak efficiency, but also degrade transient response due to the limited slew rate of the inductor current. Moreover, these topologies require numerous switches and passive components, which compromise power density and result in poor efficiency at heavy load. On the other hand, LLC resonant converters leverage transformer to achieve the large voltage conversion ratios with zero-voltage switching operation, effectively reducing switch count and enhancing power density and efficiency. However, LLC converters have limited voltage regulation capability when adjusting the switching frequency away from resonance, and also suffer from poor transient response, as will be discussed later. A sigma converter introduced in [3] [4] attempts to improve regulation by paralleling a buck converter with the LLC converter, but its transient response remains limited. In this paper, we propose a hybrid LLC resonant converter featuring a transient enhancement phase to address the transient response challenges of existing LLC converters, while simultaneously achieving efficient 48-60V to 0.8~1V conversion with improved regulation.
Emerging wearable medical sensors enabling real-time health monitoring have become increasingly important for personalized healthcare. Nearly all devices require wireless connectivity at low power to reduce size, weight, and maintenance costs (recharging or replacing the battery). Recent works in body channel communication (BCC), such as galvanic [1], magnetic resonance [2], and capacitive coupling [3], have demonstrated low power communication around human bodies, thanks to the reduced path loss. However, current BCC solutions rely on custom-designed transceivers (TRX) that are not built into commodity hardware (i.e., smartphones/smartwatches). To enable rapid deployment at scale with low cost, communication should ideally be compatible with existing infrastructure, such as WiFi and BLE. However, conventional WiFi or BLE TRXs require 10s to 100s of mW of active power; therefore, large/frequent recharged battery is still necessary.
Recent trends like AI, cloud computing, video streaming, and the internet of things create a demand for low cost, high bandwidth and highly energy efficient short-reach data links reaching data rates beyond 100 Gbit/s for the use in data centers. Transmitters (TX) utilizing a directly modulated vertical-cavity surface emitting laser (VCSEL) diodes provide adequate (BER/SNR) performance at lowest cost but have not significantly increased in speed/bandwidth in the last years [1], [3]. Utilizing PAM-4 modulation essentially doubles the data rate (in comparison to NRZ), however VCSEL drivers have not been able to exploit this, as the fastest published PAM-4 driver [2] is not outperforming the fastest NRZ driver [3]. Recent improvements have solely been achieved in the realm of power efficiency where [3], [4] were able to push the efficiency to under 1 pJ/bit at data rates of up to 80 Gbit/s. This is due to the highly nonlinear frequency behavior of the VCSEL, depicted in Fig. 1. The resonance frequency (and hence the bandwidth) changes both with modulation current (which is roughly proportional to the PAM-4 level) as well as temperature, making PAM-4 especially challenging as the ringing goes through adjacent eyes and the bandwidth change leads to eye skewing. In lab measurements, this nonlinear behavior has already successfully filtered out by the computationally expensive approach of Volterra filtering [5]. Later, equalization techniques which can be easily implemented using a lookup table (LUT) by switching the FFE coefficients data-dependent [6] were developed.
Applications such as multilane wireline links and multistream radios often require multiple low-area/cost frequency synthesizers, which motivates the use of ring-oscillator (RO)-based PLLs. However, the phase noise and jitter performance of RO-PLLs are often not sufficient to support the needs of these high-performance applications due to the high RO phase noise. Reference over-sampling PLLs (OS-PLLs), illustrated in Fig. 1 (top left), can help reduce the impact of RO noise by oversampling the reference, leading to increased loop bandwidth and suppressed out-of-band RO noise [1]. However, the achievable sampling gain is limited by the reference frequency, $\mathrm{f}_{\text{REF}}$, which is typically ≤100 MHz for practical crystal references, and, frustratingly, sampling gain also varies within a single reference period - even approaching zero near the peak of $\mathrm{V}_{\text{REF}}$ - leading to dynamically-varying loop bandwidths, deteriorated stability, and limited ability to suppress in-band noise contributors. Sub-sampling PLLs (SS-PLLs, Fig. 1 top right) [2], on the other hand, are known to have high intrinsic sampling gain by directly sampling the VCO's output, and as a result can achieve excellent in-band noise suppression, though total noise is still dominated by the RO. While techniques such as dual-path sub-sampling [3], concurrent proportional/integral gain optimization [4], cascaded DLL/RO high frequency noise suppression [2], time-based active loop filtering [5], and multi phase generator based injection locked clock multipliers (ILCM) [6], [7] can be used to suppress RO phase noise, the drastically increased power and area overhead, calibration complexity in mitigating the deteriorated spur performance, and difficulty in stabilizing their operation in these methods tend to constrain the feasible extension of loop bandwidth for RO suppression.
SRAM-based compute-in-memory (CIM) designs have shown im-pressive energy efficiency for vector-matrix multiplications of AI work-loads [1]–[9]. As many prior CIM works primarily focus on macro-level energy-efficiency, there are often big gaps between macro vs. system energy-efficiencies in real applications [10], [11]. Conventional SRAM CIM macros naturally adopt the weight-stationary (WS) dataflow, and computed partial sums are communicated to SRAM buffers outside of the CIM macro. This largely degrades the WS-CIM system energy-efficiency, especially due to frequent high-precision partial sum (Psum) read/write operations (Fig. 1). Further, while weight sparsity in AI models can be high, CIM macros with WS dataflow make zero weight skipping infeasible due to shared acti-vation and static weight storage. Previous works only support lim-ited structured (e.g. block-wise) sparsity [4], or only store non-zero weights with indices but do not have latency benefits [7]. Several systolic array designs presented skipping techniques for sparse ma-trices [12]–[14], but they all require large registers and complex con-nections, which are unsuitable for compact CIM macros. To ad-dress these challenges, this paper presents the first output-stationary SRAM digital CIM (OS-CIM) macro and system, featuring (1) an OS-CIM structure with custom single-cycle read-and-write 8T SRAM cell to store the Psum in the CIM macro and perform the accumulation locally, eliminating the expensive Psum access to SRAM buffers, (2) a dynamic look-ahead weight skipping (DLS) scheme, well aligned with OS-CIM, which achieves high latency reduction across various weight sparsity patterns and significantly improves workload balance, and (3) a runtime Psum quantization (RPQ) method to mitigate the hardware cost of high-precision accumulation.
An image sensor is one of the most important building blocks of modern electronics, such as smartphones, drones, and autonomous vehicles. The state-of-the-art image sensor captures an incredibly detailed, high-resolution image [1]–[3], however, it also generates a large amount of data, which overwhelms the downstream processing. To address this challenge, recent works have investigated in- and near-sensor data compression techniques [4]–[14]. [4] is one of the few works which demonstrated the end-to-end systems (containing pixels, compression hardware, and analog-to-digital converters [ADC]). However, it consumes a significant amount of energy of 5919 pJ/pixel, of which the analog discrete cosine transform (DCT) processor takes 58%. On the other hand, [5] proposed the analog compressor and ADC systems (no pixels). However, it also consumes a non-negligible amount of energy (404 pJ/pixel) and exhibits a limited performance of only 6 frame-per-second (fps). In contrast, [6], [7] proposed digital DCT processors, which reduce the energy consumption down to 29–126 pJ/pixel. However, they require the analog-digital conversion of every pixel, which would significantly increase the overall energy consumption.
The ubiquitous deployment of IoT applications requires low-power and low-cost wireless connectivity compatible with commodity hardware such as smartphones. Traditional IoT devices using WiFi, BLE, LTE, or 5G-NR dissipate at least mW-level power from batteries or wall power [1]–[6], which limits their lifespan or increases the hardware cost. In comparison, passive IoT tags based on backscatter communication can be compatible with existing ecosystem [7]–[15], which offer much lower hardware cost and longer life time. However, most of existing passive tags need either an incident continuous-waveform (CW) [7]–[9] or an additional codeword decoder [11]–[13], increasing the infrastructure overhead. To achieve seamless interconnection with widely-deployed hardware, both the power and data links of the passive tags should be compatible with commodity devices (such as smartphones).
