Spin qubit systems are promising candidates for Si-based quantum computing. The conventional spin-qubit cell consists of control and readout units around a quantum dot (QD) with the excess electrons functioning as spin qubits. This complicates the integration of qubits because of the many wires and extra mechanisms, such as the requirement of shuttling parts. Therefore, we propose a new structure of stacked qubits, in which the gate-all-around (GAA) channel plays the role of both control and readout, and integration of qubits is feasible by extending the commercial silicon technologies. The qubit-QDs are placed in the gate insulator between the channel region and gate electrodes, similar to floating gates. Here, we present technology computer-aided design (TCAD) simulations to show how the extra electric charges in the QD affect the channel current.
This study experimentally investigates the performance of a novel jet impingement cooler for high performance interposer package. The cooler first cools the HBM chips and then the logic chip using the same fluid stream. With water as the working fluid, the cooling solution was able to upgrade the thermal design power (TDP) of the package beyond 1 kW to a maximum of 1.86 kW at 4 L/min. The thermohydraulic performance of the cooler was then investigated in terms of the thermal resistance of all chips and the overall cooler pressure drop. The minimum thermal resistance for the logic chip was similar to 0.2 K.cm(2)/W which was obtained at 4 L/min with a modest pressure drop of 48.32 kPa. Excellent surface temperature uniformity was observed even at TDP of 1.86 kW (252 W/cm(2)) with the temperature variation being within 3 degrees C. Finally, the temperature rise across different chips was also investigated and it was revealed that the cooling scheme can be readily adapted for packages with more than 4 HBMs per logic chip and multiple such packages can be cooled using the same fluid stream for the given temperature constraints for logic chip and HBMs.
A high-speed, manufacturable, fully chiplet integration process using Face-Down bonding to 300 mm waffle-wafer and bumpless Chip-on-Wafer (COW) has been developed for the first time. The inkjet method successfully formed a thin adhesive layer on the bottom of the waffle wafer, with no voids even at a 5 mu m adhesive thickness. Over 30,000 chips with a narrow gap of 40 mu m were bonded with a misalignment of less than 10 mu m and a short bonding time of a few milliseconds per chip.
Ultra-high-density IPD capacitor is increasingly essential for high performance computing (HPC), artificial intelligence (AI) systems and mobile application compact systems in 3DFabric platform. Utilizing advanced etching and deposition techniques, Deep Trench Capacitor (DTC) features deep and narrow trenches filled with high-K dielectrics and conductive electrodes. DTC can provide significantly increased capacitance density with low equivalent series resistance (ESR) and equivalent series inductance (ESL). The miniaturization of capacitors will continue to advance Moore's law for SOC.
We address a trade-off issue between chip assembly time and positioning accuracy in a traditional pick-and-place method using self-assembly technology driven by liquid surface tension. This method allows 16-layer stacking of 50-mu m-thin chips fabricated via Plasma Dicing Before Grinding (PDBG). The surface tension of liquid droplets enables sub-50 nm alignment accuracy even with manual chip placement. By identifying key parameters such as pre-alignment position and liquid volume/distribution, we optimize the self-assembly process for High Bandwidth Memory (HBM) applications. Additionally, we discuss the effects of liquid bridges and wetting contrast between the chip surface and sidewall on multi-layer stacking.
Hybrid bonding is a crucial technology in 3D IC integration, enabling the combination of different functional chips through vertical interconnections. However, in hybrid bonding, the issue of copper oxidation during the bonding of copper metal interconnects often necessitates bonding at high temperatures, leading to thermal budget concerns. In this study, we successfully develop a novel low-temperature polymer/copper hybrid bonding process with a silver passivation layer, achieved through an area-selective deposition method. Operating within the temperature lower than 200 degrees C in an atmospheric environment, this area-selective deposition overcomes the high thermal budget challenge compared to traditional copper-to-copper bonding by mitigating copper surface oxidation. Additionally, unlike the physical vapor deposition (PVD) passivation layer, the area-selective deposition method eliminates the need for an additional photolithography process, thereby reducing both cost and processing time. This advancement positions the area-selective passivation layer as a promising candidate for low-temperature hybrid bonding technology.
Quantum computers based on superconducting qubits are advancing rapidly but face significant challenges in scaling to larger numbers of qubits while maintaining coherence and efficient addressing. Utilizing 3D integration with through-silicon vias (TSVs) presents a promising solution by enabling vertical signal routing and reducing interconnect crowding. This paper identifies Titanium Nitride (TiN) deposition via Metal-Organic Chemical Vapor Deposition (MOCVD) as an effective method for achieving conformal and superconductive coating of TSVs. A test structure is introduced to provide a rapid feedback loop for the development of this metallization. Additionally, a strategy is proposed to evaluate and interpret cryogenic resistance measurements showing transitions to superconductivity. This strategy is employed to identify the influence of deposition parameters on TiN coating on TSV sidewalls and to develop a comprehensive model explaining the deposition mechanism inside TSVs.
Thermal management is crucial for 3D-IC, as it protects chips from various issues. To provide efficient thermal management techniques, it is essential to accurately understand the heat flow within a device. In this process, thermal simulation is important, allowing precise and detailed analysis of heat conduction within the device. Therefore, we established a thermal simulation flow for 3D Si chips stacks with TSV and the accuracy of the flow was validated by comparing the simulation results with experimental measurement results.
Hybrid bonding has key advantages such as increasing the I/O bandwidth, reducing signal delay, interconnect power loss, and etc., for next generation High Performance Computing (HPC) requirements. In fact, it hybrid bonding process require the high technical hurdle, there is still a challenge that it needs high temperature such as 250 300 degC for Cu-Cu diffusion. Therefore, not only process equipment but also process materials are required to have high thermal resistance. In this paper, a Temporary Bonding De-Bonding (TBDB) tape which has "thermal resistance over 300 degC" and "easy peeling from the organic passivation" is introduced. Furthermore, it has "excellent total thickness variation (TTV)" that can provide the planarization of bonding surface with perform reliable hybrid bonding.
This study investigates the electrochemical deposition of indium thin films on copper and ruthenium seed layer for potential application in scalable 3D quantum chiplets. Our findings reveal a remarkable seed layer-dependent change in superconducting behavior: indium on copper exhibits Type-II superconductivity, while indium on ruthenium maintains Type-I superconductivity. Both systems show enhanced critical temperatures, Tc approximate to 4.3K for In/Cu and Tc approximate to 3.7K for In/Ru, compared to bulk indium (3.41K). These seed layer-dependent properties offer unique advantages for different quantum computing applications, potentially enabling tailored superconducting interconnects in 3D-integrated quantum architectures.
3D power ICs that stack Si-LSI and GaN power devices three dimensionally are promising candidates for next generation power ICs, primarily because they can minimize the power supply and realize high efficiency. However, miniaturization increases the heat generation density. One of the key problems associated with 3D power ICs is how to remove the heat. Multilayer graphene has high thermal conductivity and excellent heat removal performance. One of the most effective ways to remove heat is to directly remove it from the semiconductor chip, which is the source of heat, using multilayer graphene. In this paper, we clarify the role of multilayer graphene as a thermal interface material (TIM) and heat removal effect of multilayer graphene in 3D power ICs using thermal simulation. In addition, we propose the optimum structure using multilayer graphene, TV, h-BN, and SOI technology to realize 3D power ICs.
Die-to-wafer (D2W) technology is expected to be a key method of 3D/heterogeneous integration. Direct Transfer Bonding (DTB) was developed to solve accuracy and throughput due to chip-level handling in D2W. In this paper, Novel DTB, DTB using particle less tapes process is presented. Main results showed that novel DTB is improved in terms of bonding failure chips and void areas after DTB.
In this work, we investigate the effect of plasma hydrophilic treatment on room temperature wafer bonding using perhydropolysilazane (PHPS). Wafer bonding is a critical technique for electronics packaging, including hybrid bonding. This paper presents a method for room temperature wafer bonding via PHPS, where plasma treatment improves bond strength. Notably, N2 plasma treatment achieves higher bond strength compared to O2 plasma treatment. Surface analysis suggests that the adsorbed water introduced by plasma treatment plays an important role in enhancing bond strength. The proposed bonding method facilitates high-strength wafer bonding at room temperature.
Integrating Chiplets into advanced packaging technologies presents significant challenges in diagnosing interconnect line defects, primarily due to the immaturity of fabrication processes, reduced interconnect spacing, and increased density. In this paper, a non-destructive interconnect defect diagnosis method is proposed. Firstly, 3D TSV-RDL interconnect channels are simulated, and open and short defects are injected; utilizing S-parameters and group delays as the features, machine learning algorithms are used to realize the classification identification and localization of defects. The results show that the algorithm used can accurately identify open and short defects; in defect localization, the Mean Relative Error (MRE) of localization of the proposed method is less than 8%, and the Maximum Relative Error (MaxRE) does not exceed 13%. Compared with the related algorithms, the localization accuracy is significantly improved, providing a novel perspective for the identification and localization of defects within package interconnect lines.
Low-temperature solders are required in three-dimensional integrated circuit (3D ICs) to reduce heat input during soldering and for stacking. Sn-52mass%In alloys (Sn-In alloys) is promising because it has a melting point of 119 degrees C. However, Sn-In alloys may cause significant creep deformation at room temperature. Nanoparticle addition may control creep deformation. This study investigates the creep behavior of Sn-In alloys and tries the creep deformation control by nanoparticle addition. Experimental results showed that The creep deformation of Sn-In alloys is significant compared to other lead free solders, but this study shows that the addition of nanoparticles may improve the creep deformation of Sn-In alloys.
We demonstrate the suitability of a novel blade dicing technique introduced by DISCO that has an output comparable to that of plasma dicing, in terms of particle count and surface cleanliness - known as ‘clean dicing’. This was assessed by both a simple particle counting process and image analysis of scanning acoustic microscopy (SAM) data after wafer-to-wafer (W2W) bonding, showing minimal void count in the clean diced wafers.
In conventional processes, multichip thinning is performed after wafer-level compression molding using an epoxy mold compound (EMC). This study explores an alternative approach where multiple 300-mu m-thick chips are temporarily bonded to a glass carrier using temporary adhesives and then thinned down to 50 mu m from the backside without using EMC. This method investigates the impact of these temporary adhesives' thermomechanical properties and physical structure on the thinning process and Chemical Vapor Deposition (CVD) for via-last TSV (Through-Silicon Via) formation. This approach is particularly relevant for achieving a short turn-around time (TAT) in fabricating 3D-ICs from 2D-ICs produced through TSMC foundry shuttle services. The study demonstrates the effectiveness of temporary adhesives, particularly using a partially cured photosensitive polyimide (PSPI). The polymer is thermally stable and can be debonded using laser processing and chemical treatment after TSV formation. This PSPI significantly reduces die shift and void formation, optimizing thinning properties for 3D-IC fabrication.
An Ozone-Ethylene Radical (OER) generation technology can produce a highly active oxidizing agent of OH radicals by mixing an unsaturated hydrocarbon gas with a highly concentrated ozone gas. The OH radicals given by the OER treatment are expected to be used as a prospective surface hydrophilization technique without water rinsing. In this study, we investigate the effectiveness of the surface treatment technology OER on hybrid bonding with thermally grown SiO2, CVD-SiCN, and PVD-Cu thin films by water contact angle (WCA), AFM, and XPS. N2 plasma activation is also used before the OER treatment for comparison. OER drastically reduces the WCA of the SiCN thin films compared to the SiO2 thin film. The AFM analyses found that the surface roughness of the dielectric films is kept after the OER treatment, whereas OER slightly increases the surface roughness of Cu. XPS results suggest that the OER treatment acts on the SiO2 nitrided by N2 plasma to form Si-OH, and in addition, Cu(oh)2becomes dominant after OER processing. On the other hand, hydrophilic Cu2O mainly occupies the Cu surface before the OER treatment. Furthermore, the OER treatment on SiCN enhances oxygen composition, suggesting that OER yields more Si-OH groups by OH radicals. These results indicate that OER is a useful pretreatment method for hybrid bonding.
The role of metal density around fiducial marks (used for chip alignment) on the quality of chemical-mechanical-planarization (CMP) of Cu bond-pads/electrodes has been meticulously studied via two different layout designs. A gradual increase in the metal density between the fiducial mark and the Cu bond-pads/electrodes region has resulted in improved Cu- CMP quality. We have successfully minimized the dishing amount as well as the erosion quantity of Cu bond-pads/electrodes through optimized metal density, which are highly important to realize the high-quality and high-yield chip-to-wafer hybrid bonding.
