The eStM (embedded Select in Trench Memory) is a floating gate based non-volatile memory cell conceived, developed and industrialized by STMicroelectronics for General Purpose and Secure Microcontrollers embedded applications. Thanks to its unique architecture, the eStM cell gathers the advantages of a conventional split-gate NVM cell together with a more compact cellbit area than a typical 1T Flash Memory cell, and it is claimed to represent the scalability limit for a floating gate based NOR NVM.

This paper discusses an innovative architecture of charge storage NVM cell, which outpaces state-of-the-art in term of bit-cell area. This new concept of memory cell is used today in production for microcontrollers. After cell architecture and activation description, we will present process flow integration challenges, process optimizations and single cell characterizations.

The reliability requirements of Flash memory become more and more challenging. Flash memory technology development needs test chips to allow large statistical studies and a product-like approach. In this paper, we present a methodology of bitmap analysis to extract and follow the intrinsic and extrinsic parameters of a 40nm eFlash technology during ramp-up. This methodology is, first, based on analog bitmap acquisition on 512kB test chip, followed by correction of spatial variabilities like peripheral circuits' influences, array organization impacts and process-induced effects, to extract supplementary cell electrical parameters such as threshold voltage, transconductance or programing window. Finally, such an analysis tool enhances the advantageous properties of a test chip, its large memory cell statistics and its product-like organization, to give more reliable data. It yields more information about intrinsic cell technology weaknesses and the best way to tackle them when integrated at product level.

Today, the most widely diffused and popular non volatile memory solutions for system on chip (SOC) are Flash and EEPROM. EEPROM is especially useful for applications not requiring a large amount of memory and strongly demanding for a very high number of W/E cycles in conjunction with capability to erase small amount of memory (word size) in a short time (few ms). On the other hand the Flash solution is more attractive for applications with higher amount of memory, not requiring erasing at word level. Focusing on the field of SIM Market (Smartcard for Telecom application), the trend today is to reduce cost while keeping almost the same amount of NVM memory, with the ROM size slightly increasing due to the introduction of new software features. This caused a price pressure and forced major SIM Suppliers in the reduction of NVM cell size. In this scenario EEPROM has been scaled down to the ultimate limit for 2T architecture, showing an evident difficulty in a further scaling down perspective. At the same time, the feature of ROM personalization is also a cost, and ROM replacement with NMV would be more than welcome. This paper illustrates a solution addressing both problems, with the adoption of a scalable Flash cell and a proper Memory Architecture integrated in 90 nm CMOS technology, first in the world for SIM applications.

This paper describes a novel methodology based on UV-erased FLASH memory cells, that does not require high Voltage programming before plasma exposure. The methodology was used to evaluate a production TCpTM metal etcher. Bare wafers and wafers coated with photoresist were compared. Charging effects due to the patterning process have been identified and eliminated by proper process change.