Device scaling is critical for continuing trend of more functionality in a chip. Traditional planar CMOS scaling is increasingly difficult due to limitations in processing and material properties, device structure and reliability. In this paper we will summarize recent advances in these areas, which will enable technology scaling as per Moore's law.

In this paper we presented a retrospective on Moore's law, highlighting the salient feature of industry leading 65nm CMOS technology for high performance logic, and highlighted future challenges and approaches to overcome those.

This work looks at past, present, and future material changes for the metal-oxide-semiconductor field-effect transistor (MOSFET). It is shown that conventional planar bulk MOSFET channel length scaling, which has driven the industry for the last 40 years, is slowing. To continue Moore's law, new materials and structures are required. The first major material change to extend Moore's law is the use of SiGe at the 90-nm technology generation to incorporate significant levels of strain into the Si channel for 20%-50% mobility enhancement. For the next several logic technologies, MOSFETs will improve though higher levels of uniaxial process stress. After that, new materials that address MOSFET poly-Si gate depletion, gate thickness scaling, and alternate device structures (FinFET, tri-gate, or carbon nanotube) are possible technology directions. Which of these options are implemented depends on the magnitude of the performance benefit versus manufacturing complexity and cost. Finally, for future material changes targeted toward enhanced transistor performance, there are three key points: 1) performance enhancement options need to be scalable to future technology nodes; 2) new transistor features or structures that are not additive with current enhancement concepts may not be viable; and 3) improving external resistance appears more important than new channel materials (like carbon nanotubes) since the ratio of external to channel resistance is approaching /spl sim/1 in nanoscale planar MOSFETs.

An advanced low power, strained channel, dual poly CMOS 65nm technology with enhanced transistor performance is presented. At 1V and off current of 100nA/mum, transistors have record currents of 1.21mA/mum and 0.71mA/mum for NMOS and PMOS respectively. This industry leading 65nm technology is currently in high volume manufacturing

This paper describes the fabrication and performance of uniaxial strained silicon CMOS transistors with NiSi metal gate electrodes and ultra-thin 1.2nm gate oxide. This work offers the first comprehensive evaluation of Si CMOS devices integrating NiSi metal gate (FUSI) process with highly strained Si channels. Performance gains from FUSI gate stack and uniaxial strained Si channels are demonstrated to be fully additive and enable record high drive currents - NMOS lDSAT=1.75mA/mum, PMOS IDSAT=1.06mA/mum (VDD=1.2V, IOFF=100nA/mum). These devices have the best IDSAT vs. IOFF characteristics reported to date in the industry

We have developed a quantum anisotropic transport model for holes which, for the first time, allows mobility to be studied under both uniaxial and arbitrary stress in PMOS inversion layers. The anisotropic bandstructure of a 2D quantum gas is computed from a 6-band stress dependent k.p Hamiltonian. Our unique momentum-dependent scattering model also captures the anisotropy of scattering. A comprehensive study has been performed for uniaxial stress, biaxial stress, and their nonlinear interactions. The results are compared with device bending data and piezoresistance data, showing very good agreement.

Strained-silicon (Si) is incorporated into a leading edge 90-nm logic technology . Strained-Si increases saturated n-type and p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) drive currents by 10 and 25%, respectively. The process flow consists of selective epitaxial Si/sub 1-x/Ge/sub x/ in the source/drain regions to create longitudinal uniaxial compressive strain in the p-type MOSFET. A tensile Si nitride-capping layer is used to introduce tensile uniaxial strain into the n-type MOSFET and enhance electron mobility. Unlike past strained-Si work: 1) the amount of strain for the n-type and p-type MOSFET can be controlled independently on the same wafer and 2) the hole mobility enhancement in this letter is present at large vertical electric fields, thus, making this flow useful for nanoscale transistors in advanced logic technologies.

A leading-edge 90-nm technology with 1.2-nm physical gate oxide, 45-nm gate length, strained silicon, NiSi, seven layers of Cu interconnects, and low-/spl kappa/ CDO for high-performance dense logic is presented. Strained silicon is used to increase saturated n-type and p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) drive currents by 10% and 25%, respectively. Using selective epitaxial Si/sub 1-x/Ge/sub x/ in the source and drain regions, longitudinal uniaxial compressive stress is introduced into the p-type MOSEFT to increase hole mobility by >50%. A tensile silicon nitride-capping layer is used to introduce tensile strain into the n-type MOSFET and enhance electron mobility by 20%. Unlike all past strained-Si work, the hole mobility enhancement in this paper is present at large vertical electric fields in nanoscale transistors making this strain technique useful for advanced logic technologies. Furthermore, using piezoresistance coefficients it is shown that significantly less strain (/spl sim/5 /spl times/) is needed for a given PMOS mobility enhancement when applied via longitudinal uniaxial compression versus in-plane biaxial tension using the conventional Si/sub 1-x/Ge/sub x/ substrate approach.

This paper presents an integrated approach to modeling front end stress which has been used to investigate the main sources of stress in advanced logic technologies and how they can be used to improve device performance. The approach is illustrated with the evaluation of several technologically important stress options.

A 65nm generation logic technology with 1.2nm physical gate oxide, 35nm gate length, enhanced channel strain, NiSi, 8 layers of Cu interconnect, and low-k ILD for dense high performance logic is presented. Transistor gate length is scaled down to 35nm while not scaling the gate oxide as a means to improve performance and reduce power. Increased NMOS and PMOS drive currents are achieved by enhanced channel strain and junction engineering. 193nm lithography along with APSM mask technology is used on critical layers to provide aggressive design rules and a 6-T SRAM cell size of 0.57mum(2). Process yield, performance and reliability are demonstrated on a 70 Mbit SRAM test vehicle with >0.5 billion transistors.

A leading edge 130 nm generation logic technology with 6 layers of dual damascene Cu interconnects is reported. Dual Vt transistors are employed with 1.5 nm thick gate oxide and operating at 1.3 V. High Vt transistors have drive currents of 1.03 mA//spl mu/m and 0.5 mA//spl mu/m for NMOS and PMOS respectively, while low Vt transistors have currents of 1.17 mA//spl mu/m and 0.6 mA//spl mu/m respectively. Technology design rules allow a 6-T SRAM cell with an area of 2.45 /spl mu/m/sup 2/, while array specific design rule give the densest SRAM reported to date, the 6-T cell has an area of only 2.09 /spl mu/m/sup 2/. Excellent yield and performance is demonstrated on a 18 Mbit CMOS SRAM.

Summary form only given. We investigate scaling challenges and outline device design requirements needed to support high performance-low power planar CMOS transistor structures with physical gate lengths (L/sub GATE/) below 50 nm. This work uses a combination of simulation results, experimental data and critical analysis of published data. A realistic assessment of gate oxide thickness scaling and maximum tolerable oxide leakage is provided. We conclude that the commonly accepted upper limit of 1 A/cm/sup 2/ for gate leakage is overly pessimistic and that leakage values of up to 100 A/cm/sup 2/ are deemed acceptable for future logic technology generations. Unique channel mobility and junction edge leakage degradation mechanisms, which become prominent at 50 nm L/sub GATE/ dimensions, are highlighted using quantitative analysis. Source-drain extension (SDE) profile design requirements to simultaneously minimize short channel effects (SCE) and achieve low parasitic resistance for sub-50 nm L/sub GATE/ transistors are described for the first time.

A 180 nm generation logic technology has been developed with high performance 140 nm L/sub GATE/ transistors, six layers of aluminum interconnects and low-/spl epsi/ SiOF dielectrics. The transistors are optimized for a reduced 1.3-1.5 V operation to provide high performance and low power. The interconnects feature high aspect ratio metal lines for low resistance and fluorine doped SiO/sub 2/ inter-level dielectrics for reduced capacitance. 16 Mbit SRAMs with a 5.59 /spl mu/m/sup 2/ 6-T cell size have been built on this technology as a yield and reliability test vehicle.

The scalability of partially depleted (PD) SOI with a floating body has been evaluated to below the sub-0.25 /spl mu/m regime using transistors, ring oscillators and 4 Mb SRAMs as test vehicles. In this paper the speed and power performance of PD-SOI are compared to those of bulk for 1.8 V/sub-0.25 /spl mu/m logic applications. In addition, the 4 Mb SOI SRAM yield issues are revealed. Using the same transistor off-state leakage current limit criterion for both bulk and SOI, we conclude that PD-SOI with a floating body will provide no speed and insignificant power advantage over bulk for sub-0.25 /spl mu/m logic applications.