We propose a TCAD-machine learning coupled approach that combines a TCAD tool (Charon), optimization/uncertainty quantification tool (Dakota), surrogate models, and Bayesian learning capabilities. The coupling approach is used for accurate modeling and calibration of total ionizing dose (TID) induced threshold voltage (Vth) shifts in Commercial-Off-The-Shelf (COTS) semiconductor devices and to develop physics-informed TID compact models. This versatile approach is applied to model the TID effect in an exemplar COTS 3.3 kV SiC power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). With the Charon-Dakota coupling, we can determine key device geometry and doping values based on device physics, which are difficult to obtain or not available for COTS devices but important for TCAD simulation; additionally, we can efficiently generate thousands of simulation results in a large parameter space, which makes it possible to develop data-driven surrogate models and perform Bayesian calibration. Utilizing the full tool-coupling approach, we achieve calibrated TCAD simulation models that accurately capture the average TID-induced Vth shifts behavior with total doses and Vth shifts saturation at high doses as observed in experimental data. More importantly, the calibrated TCAD simulations are obtained with determined TID model parameters (e.g., hole trap density and capture cross section) values that contain well quantified uncertainties. Furthermore, we can isolate and quantify the noises that are not captured by the TCAD models but exist in the measured data due to measurements and devices variabilities. Lastly, the calibrated surrogate models are used to develop physics-informed TID compact models. The method is generalizable to other devices and/or radiation conditions with little modifications and can provide well-determined uncertainties.

Deposition techniques, like atomic layer deposition (ALD), are used to form high-quality dielectrics for GaN-based metal–oxide–semiconductor (MOS) gate structures due to the lack of a reliable thermal oxide in GaN. Moreover, interfacial GaOx from pre-existing native oxides is thought to adversely impact channel carrier dynamics and induce undesired threshold voltage shifts in GaN-based MOS gate structures. Exposure of the GaN surface to the trimethylaluminum (TMA) precursor prior to standard alumina ALD decreases the native oxide layer on GaN, but the extent of chemical modification has not been well studied in the context of interface composition in a MOS gate structure. Herein, we compare annealed 55 nm Al2O3 dielectric films on GaN grown using either a water-first ALD process or a process including sequential pulses of TMA immediately before the initiation of Al2O3 ALD. Time-of-Flight Secondary Ion Mass Spectrometry measures differences in the interfacial GaOx content between each ALD film. It also detects surface contaminant species like Si, F, S, and C. Furthermore, we report the formation of an AlN species at the Al2O3/GaN interface, which is more prominent for the film grown using the TMA pre-pulse step. In general, this work demonstrates that the TMA pre-pulse step is an effective strategy for cleaning substrate surfaces prior to ALD.

Simultaneous high-humidity, high-temperature, reverse bias testing, otherwise known as H3TRB testing, is conducted to compare the accelerated failure of vertical 1700-V silicon carbide MOSFETs provided by two well-known manufacturers. A pronounced drain-to-source leakage is observed in the tested devices from only one of the manufacturers. Interrupted test measurements reveal that the degradation mode occurs relatively quickly (i.e., < 100 hours) for the failed devices. A post-test bake-out returns all the tested devices to nominal behavior and strongly suggests that the failure mechanism is associated with surface charge buildup in or below the passivation layer. Scanning electron microscopy and scanning capacitance microscopy imaging reveal significant design differences in the edge termination structure for each device set. The difference in design choice demonstrates how humidity robustness may be achieved through device-level surface charge mitigation strategies rather than relying on a hermetic encapsulant.

Vertical gallium nitride (GaN) power devices continue to garner interest in multiple power conversion applications requiring a medium-voltage (1.2 – 20 kV) capability. Currently, silicon carbide (SiC) is addressing this voltage range, however, with a comparable critical electric field and superior mobility, GaN is expected to offer advantages in applications where fast switching and avalanche breakdown response times are desired. While uses in electric vehicles, solid-state transformers, and renewable energy conversion are being actively explored, the potential of a vertical GaN device for electric grid protection in the form of an electromagnetic pulse arrestor is a unique proposition that requires very fast transient capabilities (<1 µs pulse widths with rise-times on the order of 10 ns). However, vertical GaN devices are significantly less mature than present SiC offerings. Specifically, low-doped, thick epitaxial growth of GaN via metal-organic chemical vapor deposition (MOCVD) still presents many challenges, and advancements in processing, manufacturability, and failure analysis are needed. In this work, we describe our efforts to address the above issues and advance the state-of-the-art in vertical GaN PN diode development. We have successfully demonstrated an MOCVD-grown, 50 µm thick, low-doped (<10 15 cm -3 ) drift region on a GaN substrate that was processed into relatively large-area (1 mm 2 ) PN diodes capable of achieving a 6.7 kV breakdown. Temperature-dependent breakdown was observed, consistent with the avalanche process. The devices consisted of a 4-zone step-etched junction termination extension (JTE), where the breakdown region was visualized via electroluminescence (EL) imaging. Ongoing work aims to scale the current capability of the medium-voltage diodes through a parallel interconnect design that negates defective or poor performing diodes. Further investigation of edge termination structures was explored using a bevel approach, where we studied the relationship between the bevel angle and p-doping. It was found that a very shallow angle of only 5° accompanied by a 500 nm p-region consisting of 3×10 17 cm -3 Mg concentration resulted in a consistent 1.2 kV breakdown for an 8 µm thick, 1.6×10 16 cm -3 doped drift region. EL imaging confirmed uniform breakdown, and temperature dependence was demonstrated. The bevel approach was then implemented on a diode structure with a 20 µm thick drift region capable of 3.3 kV breakdown, where an unclamped inductive switching (UIS) test was performed to evaluate the impact of a field plate design on avalanche uniformity and ruggedness. A parallel effort to establish a foundry process for vertical GaN devices has been underway. Initially, this focus was on comprehensive studies of GaN wafer metrology using capacitance-voltage (C-V) mapping, optical profilometry, and x-ray diffraction (XRD) mapping. A machine learning algorithm was implemented to identify defective regions and produce a yield prediction for each GaN wafer prior to processing. A hybrid edge termination structure consisting of implanted guard rings (GR) and JTEs was developed in coordination with a controlled experiment that varied the anode thickness, and therefore the remaining p-GaN after implantation. It was observed that thinner p-GaN regions under the JTE/GR region resulted in a significant (>100x) reduction in leakage current under reverse-bias conditions. This process has resulted in 1.2-kV-class devices with up to 18 A forward current for a 1 mm 2 device with a specific on-resistance of 1.2 mOhm-cm 2 . The foundry effort has since been extended to 3.3-kV-class devices that utilize 25 µm thick drift layers with ~2-4×10 15 cm -3 doping. These devices have demonstrated up to 3.8 kV breakdown with leakage currents <1 nA up to 3 kV. More than 40 wafers have been processed to date, resulting in >20,000 devices. Statistical variations in I-V and C-V characteristics will be discussed. Packaging process development and analysis are underway to develop electrical stress procedures and identify fundamental failure mechanisms. Finally, a pulse arrested spark discharge (PASD) setup, capable of up to 15 kV pulsed operation in 100 V steps, was implemented to quantify the time response of avalanche breakdown. Initial results on a packaged 800 V device showed a ~1 ns response time during breakdown, which reinforces the potential EMP grid protection applicability. This work was supported by the ARPA-E OPEN+ Kilovolt Devices Cohort directed by Dr.Isik Kizilyalli. Sandia National Laboratories is a multi-mission laboratory managed and operated by National Technology & Engineering Solutions of Sandia, LLC, a wholly owned subsidiary of Honeywell International Inc., for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-NA0003525. This paper describes objective technical results and analysis. Any subjective views or opinions that might be expressed in the paper do not necessarily represent the views of the U.S. Department of Energy of the United States Government.

Characterizing interface trap states in commercial wide bandgap devices using frequency-based measurements requires unconventionally high probing frequencies to account for both fast and slow traps associated with wide bandgap materials. The C−ψS technique has been suggested as a viable quasi-static method for determining the interface trap state densities in wide bandgap systems, but the results are shown to be susceptible to errors in the analysis procedure. This work explores the primary sources of errors present in the C−ψS technique using an analytical model that describes the apparent response for wide bandgap MOS capacitor devices. Measurement noise is shown to greatly impact the linear fitting routine of the 1/CS∗2 vs ψS plot to calibrate the additive constant in the surface potential/gate voltage relationship, and an inexact knowledge of the oxide capacitance is also shown to impede interface trap state analysis near the band edge. In addition, a slight nonlinearity that is typically present throughout the 1/CS∗2 vs ψS plot hinders the accurate estimation of interface trap densities, which is demonstrated for a fabricated n-SiC MOS capacitor device. Methods are suggested to improve quasi-static analysis, including a novel method to determine an approximate integration constant without relying on a linear fitting routine.

This work reports on the optimal dose for a step-etched single-zone junction termination extension by means of a multi-point study on etch depth. Breakdown and device characteristics are reported on over one hundred devices for each dataset to determine a statistically significant representation of the population. Electroluminescence imaging during avalanche breakdown confirms the point at which the JTE switches from full depletion to partial depletion, which corresponds to the maximum breakdown.

Wide-bandgap semiconductors have a significant advantage over conventional Si-based electronics by leveraging materials properties to achieve higher breakdown voltage, lower on-resistance, and high-frequency operation. Gallium nitride (GaN) is of interest for vertical device architectures but directly competes with the already established silicon carbide (SiC) power devices. In the case of vertical GaN rectifiers which are unipolar figure-of-merit limited, the materials advantage of GaN provides a modest gain in terms of critical electric field and very slight gains in bulk mobility and saturation velocity, while being at a disadvantage in terms of thermal conductivity compared to SiC. However, despite still being a very immature technology, vertical GaN MOSFETs have demonstrated channel mobilities upwards of 200 cm2/V·s, over three times that of SiC-based MOSFETs. For 1200V-class devices, channel mobility directly contributes to a significant portion of device on-resistance, and it is therefore expected that vertical GaN MOSFETs would offer a substantial performance advantage compared to SiC MOSFETs. Despite this, the development of vertical GaN devices that demonstrate this theoretical potential faces many challenges. Several fundamental limitations exist within the manufacturing process that prohibit GaN devices from directly mirroring the design rules for similar SiC devices. In this talk, we will discuss several key design concepts recently developed for vertical GaN MOSFETs which serve to address several critical issues for GaN. Limitations in selective-area doping for GaN provide an additional challenge in designing edge termination structures, advanced features that protect the gate dielectric during the blocking state, and provides restrictions on minimizing cell pitch. Proper edge termination design is required to reach an avalanche voltage near the theoretical limit and avoid early breakdown. We present an optimized design point for the edge termination with a good match between theoretical and experimental data using a step-etched junction termination extension. Despite a well-designed edge termination, early breakdown will occur in the gate dielectric at the bottom of the gate trench due to field crowding in the dielectric at high blocking voltages. We propose a new method for protecting the gate dielectric by means of a buried field shield formed by an etch-and-regrowth process. Experimental data shows this gate dielectric failure can occur as early as 1/3rd of the designed blocking voltage. The field shield design is shown in simulation to sufficiently reduce the electric field in the gate dielectric to below 4 MV/cm with minimal or no derating of the device depending on geometry of the shield. Additional methods will be presented on new techniques to minimize cell pitch, a critical factor necessary to compete against SiC. Cell pitch minimization not only reduces on-resistance and gate-charge trade-offs, but it is also a driving factor to reduce cost and increase die density on wafer. Finally, techniques have been developed for advanced metal contact designs specific to the trench MOSFET, which further aid in reducing cell pitch. This work was supported by the Electric Drivetrain Consortium managed by Susan Rogers of DOE’s Vehicle Technologies Office. Sandia National Laboratories is a multi-mission laboratory managed and operated by National Technology & Engineering Solutions of Sandia, LLC, a wholly owned subsidiary of Honeywell International Inc., for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-NA0003525. This paper describes objective technical results and analysis. Any subjective views or opinions that might be expressed in the paper do not necessarily represent the views of the U.S. Department of Energy or the United States Government.

This work provides the first demonstration of a multipoint fit from theory to experiment for step-etched junction terminations on vertical gallium nitride (GaN) devices. Viable edge termination methods in GaN are limited due to challenges with selective-area doping. We report on a study that determines the optimal charge in the junction termination extension (JTE) of a GaN-based p-n diode to aid in the design of multizone JTEs. Experimental results show a step-thickness offset compared to theoretical prediction, which is attributed to plasma-induced etch damage, as well as variation in passivation-related charge, surface charge, and doping profile variations. Results are supported by electroluminescence imaging, which confirms the match from theory to experiment.

Wide-bandgap semiconductors have a significant advantage over conventional Si-based electronics by leveraging materials properties to achieve higher breakdown voltage, lower on-resistance, and high-frequency operation. For electric vehicle drivetrains, this translates to higher efficiency and power density, resulting in more miles driven per charge. This move towards wide-bandgap power electronics is necessary to achieve the U.S. Department of Energy (DOE) power electronics density target of 100 kW/L. Vertical gallium nitride-based power devices are expected to exceed Si and even SiC-based systems with the promise of increased performance and power density. Compared to lateral GaN devices, a vertical topology promotes more efficient scaling towards high-power applications, where both high voltage and high current are necessary. This talk describes our team’s effort towards developing vertical GaN MOSFETs. The results of Sandia’s first-generation device demonstrator serve as a milestone in the path of producing devices rated for 1200-V and 100-A operation. The vertical GaN trench MOSFET is unique compared to Si- or SiC-alternatives in that the doped layers comprising the source and body regions are grown by epitaxy rather than formed by ion implantation. Challenges with selective-area doping in GaN add additional complexity to the design of a trench MOSFET. In addition, the lack of a high-quality native oxide in GaN means that the gate dielectric must be deposited rather than thermally grown. The devices produced at Sandia rely on atomic-layer-deposited thin films for the gate dielectric (primarily Al2O3 or SiO2). First-generation results demonstrate devices capable of 400 mA/mm drain current, 108 on/off ratio, and a positive threshold voltage near 8 V. More recently, devices capable of blocking 500 V in the off-state have been demonstrated. Device failure in the off-state results from high fields in the gate dielectric, which can be minimized by reducing the trench etch depth or by increasing the voltage rating of the drift region. However, further shielding of the gate dielectric to achieve substantially higher off-state voltages requires significant changes to the device architecture which are reliant on selective-area doping. In addition, device-killing defects either from the starting substrate, the epitaxy, or defects introduced during processing limit yield for large-area devices and present a substantial obstacle to scale devices for high-current operation. Hence, methods for reducing cell pitch and increasing packing density are highly valued. In this talk, we will discuss the path forward for achieving higher breakdown voltages and high-current operation using GaN-specific strategies to achieve better performing devices, as well as some of the challenges for vertical GaN development. This work provides a foundational platform for developing next-generation power electronics that employ wide bandgap, gallium nitride semiconductors. This work was supported by the Electric Drivetrain Consortium managed by Susan Rogers of DOE’s Vehicle Technologies Office. Sandia National Laboratories is a multi-mission laboratory managed and operated by National Technology & Engineering Solutions of Sandia, LLC, a wholly owned subsidiary of Honeywell International Inc., for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-NA0003525. This paper describes objective technical results and analysis. Any subjective views or opinions that might be expressed in the paper do not necessarily represent the views of the U.S. Department of Energy or the United States Government. Figure 1

This study analyzes the ability of various processing techniques to reduce leakage current in vertical GaN MOS devices. Careful analysis is required to determine suitable gate dielectric materials in vertical GaN MOSFET devices since they are largely responsible for determination of threshold voltage, gate leakage reduction, and semiconductor/dielectric interface traps. SiO 2 , Al 2 O 3 , and HfO 2 films were deposited by Atomic Layer Deposition (ALD) and subjected to treatments nominally identical to those in a vertical GaN MOSFET fabrication sequence. This work determines mechanisms for reducing gate leakage by reduction of surface contaminants and interface traps using pre-deposition cleans, elevated temperature depositions, and post-deposition anneals. Breakdown measurements indicate that ALD Al2O3 is an ideal candidate for a MOSFET gate dielectric, with a breakdown electric field near 7.5 MV/cm with no high temperature annealing required to increase breakdown strength. SiO 2 ALD films treated with a post deposition anneal at 850 °C for 30 minutes show significant reduction in leakage current while maintaining breakdown at 5.5 MV/cm. HfO 2 films show breakdown nominally identical to annealed SiO 2 films, but with significantly higher leakage. Additionally, HfO 2 films show more sensitivity to high temperature annealing suggesting that more research into surface cleans is necessary to improving these films for MOSFET gate applications.

This work provides the first demonstration of vertical GaN Junction Barrier Schottky (JBS) rectifiers fabricated by etch and regrowth of p-GaN. A reverse blocking voltage near 1500 V was achieved at ~ 1 mA reverse leakage, with a sub 1 V turn-on and a specific on-resistance of 10 mΩ-cm2. This result is compared to other reported JBS devices in the literature and our device demonstrates the lowest leakage slope at high reverse bias. A large initial leakage current is present near zero-bias which is attributed to a combination of inadequate etch-damage removal and passivation induced leakage current.