The extraction of ESD parameters and a Transient Safe Operating Area (TSOA) based on on-wafer HBM-IV measurements with voltage and current waveform capturing are introduced. The HBM parameters provide an easy way to get valuable insights in the transient device operation of ESD protection devices, circuits and their safe operating area under HBM stress conditions.

The self-protection capability (SPC) of integrated power arrays in ESD regimes has been studied for the case of integrated 100 V NLDMOS arrays in a BCD process. A new practical methodology for array comparison has been experimentally validated in order to take into account both gate coupling and avalanche current effects. Using TLP and electrical test methods, two orders of magnitude improvement of SPC has been demonstrated by implementation changes to array design. The effects of the Pbody shading and the drain region design have been quantified and analyzed by numerical simulation, and their physical nature has been discussed.

As a first step towards correlation of system level ESD robustness based on component level ESD results, on-wafer Human Metal Model (HMM) measurements are compared with on-wafer HBM for a wide range of devices in various process technologies. A device level System to Component level Correlation Factor (SCCF) is defined and can range from 10 to 150% based upon physical failure mechanisms. Five main categories are defined independent of process technology.

Charged device model (CDM) electrostatic discharge (ESD) stress is a major concern for inductor-based ESD protection strategies for RF circuits processed in advanced nano-CMOS technologies. The CDM robustness of such protection methodology is investigated in this paper based on very-fast transmission line pulse (VFTLP) measurements. Its applicability is discussed for future technologies and RF applications.

The turn-on behavior of high voltage ESD devices is studied during HBM ESD stress. Two phenomena are experimentally observed for two different HV processes and several device architectures: a voltage overshoot up to two times of the TLP triggering voltage, and a current overshoot several times the nominal HBM current.

Based upon measurements of the HBM waveforms of DeMOS-SCR devices, the voltage overshoot during turn-on is studied as a function of device architecture and gate sub-circuit. It has been demonstrated that, in general, the overshoot voltage does not correlate to the TLP triggering voltage, but can be controlled in a wide range both at the device level and at the gate sub-circuit level by modifying blocking junction breakdown voltage, gate coupling and displacement current density in the internal parasitic BJT.

The residual voltage across the ESD snapback protection device after its turn-off is one of the key parameters that must be considered for efficient ESD protection design. Turn-off characteristics of various snapback devices (5VNMOS, 5V LVTSCR and 12V DeMOS-SCR), are analyzed with experimental data for the first time and it is demonstrated that the residual voltage after turn-off is a unique parameter and depends on the type of ESD device, its architecture and layout. The residual voltage after turn-off can vary in a wide range from holding voltage to DC breakdown voltage and is a function of the ESD pulse amplitude. The underlying physical mechanism causing the waveform behavior is discussed in detail.

This paper addresses the ESD reliability issues in RFICs, focusing on the technology impact on the device and design. We also present the basic RF ESD protection methods used in industry. Presents the general topology of a 5 GHz LNA, which is protected using several ESD protection methodologies, and describes the 90 nm CMOS process technology used for the fabrication of the LNA. The measurement procedures used for the evaluation of stand-alone devices and LNAs are described. The ESD performance of standard ESD protection devices is reviewed and presents results and discussions on the ESD reliability of various ESD protection methods employed from the device point of view, followed by an outlook on the future RF ESD challenges, and conclusions.

ESD protection strategies utilized in RF circuit applications in CMOS and BiCMOS technologies are investigated and the results are presented in this paper. The conventional approach using diodes with power clamp is compared with novel approaches such as plug-and-play passive elements and full or partial circuit-ESD co-design. The trade-offs are discussed from both RF and ESD point of views. Common problems as parasitic ESD current discharge paths and voltage overshoot are discussed and solutions are proposed

To reduce the cycle time and the cost of the design of ESD tolerant over-voltage I/O cells, a methodology for pre-silicon ESD protection optimisation is described, based on Technology Computer Aided Design (TCAD) (device level) and compact (circuit level) simulation studies. Using this methodology, first time right ESD tolerant over-voltage I/O cells were designed in a silicided 0.25 mum CMOS dual gate-oxide process. The methodology consists in a precise TCAD process calibration, a cascoded snapback NMOS compact model definition valid under ESD conditions, a model parameter extraction based on TCAD data and, finally, circuit level optimisation of the I/O protection circuits. Very good agreement was achieved between the simulated pre-silicon characteristics and the experimental behaviour of the I/O protection circuits. (C) 2004 Elsevier Ltd. All rights reserved.

This paper presents an equivalent circuit snapback model for the ESD domain operation of merged cascoded NMOS devices. The model reflects the specific breakdown operation of the structure at different gate bias conditions. An example for optimisation of the ESD behaviour of an output driver, utilising this protection device, is presented.

Nanopotentiometry is a scanning probe microscopy (SPM) technique providing insight in the actual working behavior of semiconductor devices under operation. In nanopotentiometry, a conductive SPM tip is used as a voltage probe in order to measure the distribution of the electrical potential on the cross section of an operating device. The information thus provided is complementary to carrier profiling and is a method for the calibration of device simulations. The suitability of alternative SPM techniques for studying ultrashallow devices under operation is examined. Measurements have been carried out in deep submicron complementary metal–oxide–semiconductor devices. The impact of the changes in the doping profile on the potential distributions has been explored using simulations and experimental results. Due to further improvements in sample preparation and measurement methodology, the response of the devices to variable bias conditions could be studied in more detail. The formation of the conductive channel underneath the gate was investigated and compared to device simulations.

We have imaged several n-type metal-oxide-semiconductor transistors with different source and drain architectures to assess the feasibility of extracting useful figures of merit, such as the effective channel length of a device, from the data. By varying the dc bias on the sample we observe a shift of the junction position in the image and consider how best to interpret a set of voltage dependent images produced for a single sample. Careful attention is paid to the effects of surface variation from sample preparation and tip wear during an experiment by considering the scanning capacitance microscopy signal in the substrate as a function of applied dc bias.

In this study the origin of the leakage current of n(+)p diodes and the impact of process conditions on the leakage current is investigated. The influence of isolation modules, namely, conventional local oxidation of silicon (LOCOS) vs. polybuffered LOGOS, and different junction annealing conditions, namely, furnace anneal and rapid thermal anneal, on the diode leakage current is discussed. The diode leakage current level distribution over a wafer is very sensitive to specific processing steps, such as active area definition. For large peripheral diodes in p-type substrate or in p-well, the leakage current strongly depends on junction annealing conditions. The diodes processed with furnace anneal have one order of magnitude lower leakage currents compared to the diodes with rapid thermal anneal. This difference in leakage current is due to different surface generation velocities at the silicon-oxide isolation interface. (C) 1999 The Electrochemical Society. S0013-4651(98)02-067-9. All rights reserved.

Different two-dimensional (2-D) carrier profiling tools, based on contact-mode atomic force microscopy (AFM), have been used to investigate the details in the lateral and vertical distribution of the carriers in nMOSFET devices with identical channel profile (4e17 atoms/cm/sup 3/) and gate oxide thickness (5.5 nm) but with different S/D architectures, all relevant for 0.25 /spl mu/m CMOS technology. These characterization techniques are: scanning capacitance microscopy (SCM) and scanning spreading resistance microscopy (SSRM). Two typical 2-D case studies are presented. In the first one, the effective gate length is determined. The measured values are compared with the ones measured by extraction from the electrical characteristics using a modified shift and ratio method. In the second study, the vertical channel profile through the centre of the gate is studied as a function of the gate length. Here, for the first time, transient enhanced diffusion (TED) effects are directly observed. This type of profile information is not accessible using standard 1-D profiling techniques such as SIMS, SRP, or C-V profiling.

Transferring a CMOS circuit to a foreign substrate can be accomplished by bonding a processed silicon wafer to the substrate and subsequently thinning the silicon wafer. This paper presents both anodic bonding and adhesive bonding and evaluates their potential for circuit transfer.

The possibilities and limitations of non-destructive extended defect characterization techniques, i.e. X-ray topography, carrier recombination imaging and laser scattering tomography are illustrated by a case study whereby a dislocation problem occurred during the local isolation step of a CMOS compatible diode process. It is shown that the diode yield is correlated with the presence of dislocations observed after the full process. The ''in process'' application of the techniques is illustrated by investigating defect formation after different local isolation processes.

Reports on a transfer technique for CMOS circuits based on a newly developed bonding technique, namely wafer scale adhesive bonding using epoxies. The circuit transfer sequence consists of three steps: bonding a CMOS processed SIMOX wafer to a Pyrex glass wafer, thinning the SIMOX wafer down to the buried oxide and exposing the contact pads. A test chip was designed to evaluate the impact of circuit transfer on the device performance. Measurements have shown a slight increase in leakage current and a small change of threshold voltage due to stress induced by the circuit transfer.

Transmissive single crystal AMLCD light valves have recently drawn much attention for application in flat panel displays. The active matrix circuits are fabricated on SIMOX wafers and then transferred to glass. Circuit transfer consists in bonding a CMOS processed SIMOX wafer to a Pyrex glass substrate, thinning the SIMOX wafer and opening the contact pads. The pixel electrodes are made in polysilicon to allow standard CMOS processing. This paper discusses the transparency of the poly electrode and evaluates the potential of anodic bonding and adhesive bonding for circuit transfer. A major challenge for anodic bonding is the protection of the device dielectrics against the high voltages applied during bonding. A test chip was designed to investigate different ways of circumventing breakdown of the dielectrics. A method for adhesive bonding is discussed that assures good uniformity of the thickness of the epoxy layer and avoids the inclusion of air bubbles. It is demonstrated that the epoxies are resistant to the chemicals used for thinning the silicon substrate.