This work reports the progress in source/drain (S/D) epitaxy development for nanosheet-based monolithic complementary field effect transistors (mCFET). S/D processes which were set-up for bulk finFET devices can be easily transferred to mCFET devices. Owing to the complicated integration and small dimensions of the highly scaled structures however, more attention is required for the pre-epi cleaning of the exposed channel interfaces and for the additional defectivity that arises from the merging of individual epitaxial growth fronts. Low-temperature epi processes can be structurally integrated in mCFET devices, to further reduce the transistor access resistance components and comply with thermal budget limitations.

The complementary field-effect transistor (CFET) is an attractive device architecture for beyond 1 nm CMOS technology nodes where n- and p-MOS nanosheet devices are placed on top of each other [1-3]. In the present paper, we discuss the progress in source/drain (SD) epitaxy development for nanosheet and monolithic CFET (mCFET) devices. A schematic cross-section of a mCFET stack is shown in Figure 1, in the case of a Metal-Diffusion-first (MD-first) integration scheme [3]. In this case, the p-MOS device is made first, leading to a bottom SiGe:B (B-SiGe:B) SD epi layer. The n-MOS device with top Si:P (T-Si:P) SD is placed on top of the p-MOS, which requires an isolation layer between the two devices. Figure 2 shows cross-section transmission electron microscopy (X-TEM) examples for the integration of a co-flow SiGe:B layer [4] in nanosheet and CFET structures with 48 nm and 60 nm contacted poly pitch (CPP) respectively. In case of multiple sheets (Figure 2(a)), the SiGe:B growth happens from the different Si sheets and from the Si bulk. Twin defects can be observed due to the merging of neighboring and opposing sheets. For the bottom SD in CFET structures with single nanosheets (Figure 2(b)), the majority of the SiGe:B is grown from the Si bulk which then merges with the growth fronts from the single sheets. For the pre-cleaning of the nano-sheets before epi growth, we rely on a combination of wet and low-temperature in situ PreviumTM clean [5]. A pre-epi bake is omitted to avoid dummy gate crystallization. Figure 2(c) summarizes specific Ti/SiGe:B contact resistivity (rc) levels obtained using the circular transmission line method (CTLM) for stacks based on conventional co-flow and low-temperature (LT) SiGe:B processes [6-8]. Results are plotted as a function of the material resistivity (r). A lowest rc of ~ 2×10-9 Ω.cm2 is demonstrated with LT-Si0.5Ge0.5:B (active B concentration [B]act = 2.5×1021 cm-3), which is ~ 50% lower than values obtained with conventional Si0.4Ge0.6:B, for which lower [B]act are obtained. In the present paper we will further discuss the progress towards using LT-SiGe:B cyclic deposition etch (CDE) processes in nanosheet-based devices to reduce the access resistance. X-TEM examples of the integration of T-Si:P SD in a CFET structure with 60 nm CPP are shown in Figure 3. A conventional high-temperature (HT)-Si:P [9] (Figure 3(a)) is compared with a LT-Si:P variant (Figure 3(b)). The LT-Si:P process used here is a CDE process running at 525ºC, which combines deposition with a higher order Si precursor and a HCl/GeH4 based etching steps to enable the selective epitaxial growth (SEG) of Si:P SD [10-13]. Figure 3(c) plots the specific resistivities obtained for Ti/Si:P contacts as a function of the active P-concentration ([P]act) as determined from micro-Hall measurements [6,7,13]. For the HT-Si:P process, the doping activation after epitaxy is relatively poor (10%-15%) and post epitaxy spike or laser anneals are typically used to increase the active concentration and decrease the contact resistivity. When moving to LT-Si:P processes with temperatures below 500ºC [14], [P]act can be increased up to ~ 1×1021 cm-3 and the contact resistivity reduced to ~ 2×10-9 Ω.cm2. In the present paper we will further discuss the progress of using LT-Si:P CDE processes in nanosheet-based devices and enable a benchmark of recently developed SD selective epitaxial growth options for the consistent fabrication of performant CFET devices. Acknowledgements This project has received funding from the ECSEL Joint Undertaking (JU) under grant agreement No 101007254. The JU receives support from the European Union’s Horizon 2020 research and innovation programme and Netherlands, Germany, France, Czech Republic, Austria, Spain, Belgium, Israel. The imec core CMOS program members, local authorities and the imec pilot line are acknowledged for their support. [1] N. Horiguchi et al, IEDM2023, 29.1. [2] H. Mertens et al., VLSI2023, 1.3. [3] V. Vega et al., accepted for IITC2024. [4] A. Hikavyy et al., ECS Trans., 104 (4), pp.139-146, 2021. [5] H. B. Profijt et al., ICSI, p.143, 2015. [6] C. Porret et al, IEDM2022, 34.1. [7] C. Porret et al., SSDM2023, p. 287. [8] R. Khazaka et al., 2nd ECS Meet. Abstr., G03-1187, 2022. [9] E. Rosseel et al., ECS Trans. 75(8), pp.347-359, 2016. [10] N. Loubet et al., Thin Solid Films 520, pp.3149-3154 (2012). [11] J.M. Hartmann et al., Semicond. Sci. Technol. 28, p.025018 (2013). [12] E. Rosseel et al., ECS Transactions, 64 (6), pp.977-987, 2014. [13] R. Khazaka et al., 2020 ECS Meet. Abstr., MA2020-02, 1734, 2020. [14] E. Rosseel et al., ECS Transactions, 109 (4), pp.93-98, 2022. Figure 1

The surrounding-gate-transistor (SGT) is a vertical gate-all-around device with a new design to exploit natural area gain for further scaling the SRAM size beyond N5 node. One of the benefits in SGT is it can fully decouple the dependency of the gate length (Lg) and the source/drain (S/D) contact size from the contact gate pitch (CGP) scaling, which is seen as a hard limit for the conventional scaling. To fully realize the benefit of area gain and Lg scaling independent from lithography, the patterning challenges of 3D vertical device structure must be resolved. In this paper, we report the MOL patterning challenges in SGT device fabrication, such as Metal recess process, Bottom Contact formation (VBG), Cross point formation (XC), Top electrode (TE) patterning.

In this study, we explored the key properties and functionalities of plasma enhanced atomic layer deposition (PEALD) SiNx films, synthesized using different deposition temperatures (500–550 °C) and plasma conditions (lower and higher), both on 300 mm blanket Si and on several integrated 3D topology substrates, at the thicknesses relevant for diverse nanoscale applications. Our study shows that with an increase of temperature (500–550 °C), a small reduction in HF wet etch rate (1.1–0.69 nm/min), and H content (9.6% vs 7.4%) was observed. When using higher plasmas, significant improvements in blanket properties were observed. The films were denser (2.95 g/cm3), exhibited lower H content (2.4%), showed better etch rates (0.39 and 0.44 nm/s for HF and CF4 based), and SiNx grew without any nucleation delay on alternative Si1−xGex channel surfaces. The vertical and lateral conformality was found to be similar and appears not to be impacted with the plasma conditions. Extensive steam oxidation barrier studies performed at the sidewalls of different aspect ratio lines showed the PEALD SiNx liner scaling potentiality down to 1 nm when deposited using higher plasma. In addition, the outer gate and inner spacer properties were found to be superior (with lower loses) for higher plasma films when subjected to several dry etch, strips, and H3PO4 chemistries. The outstanding conformality (90%–95% on aspect ratios ≤10:1) combined with excellent high end material properties in the ultrathin regimes (1–10 nm) corroborate the virtue of PEALD SiNx toward integration in scaled down and advanced nanoelectronics device manufacturing.

In order to integrate k=2.0 p-OSG dielectric materials into the next generation of interconnects, the porous material has to be sealed against metal barrier precursor. For this purpose, the combination of pore stuffing and SAMs was engineered on patterned structures to achieve sealing with minimal plasma damage. First a pore stuffing (P4) approach was implemented to mitigate the plasma damage and to confine the reaction sites to the top surface. Then self-assembled monolayers (SAMs) were deposited from 11-cyanoundecyltrichlorosilane (CNSAM) or (3-aminopropyl)-trimethoxysilane (APTMS) precursor, followed by TiN metal barrier deposition via plasma enhanced-atomic layer deposition (PE-ALD). Pore sealing efficiencies and k value of these samples were benchmarked against standard back end of line (BEOL) CF4 plasma.

In this work we provide a comprehensive evaluation of a novel, low-resistance Co–Al alloy vs W to fill aggressively scaled gates with high aspect-ratios [gate height (H gate) ∼50–60 nm, gate length (L gate) ≥20–25 nm]. We demonstrate that, with careful liner/barrier materials selection and tuning, well-behaved devices are obtained, showing: tight gate resistance (R gate) distributions down to L gate∼20 nm, low threshold voltage (V T) values, comparable DC and bias temperature instability (BTI) behavior, and improved RF response. The impact of fill-metals intrinsic stress, including the presence of occasional voids in narrow W-gates, on devices fabrication and performance is also explored.

This work reports on aggressively scaled replacement metal gate, high-k last devices (RMG-HKL), exploring several options for effective work function (EWF) engineering, and targeting logic high-performance and low-power applications. Tight low-threshold voltage (V T) distributions for scaled NMOS devices are obtained by controlled TiN/TiAl-alloying, either by using RF-physical vapor deposition (RF-PVD) or atomic layer deposition (ALD) for TiN growth. The first technique allows optimization of the TiAl/TiN thicknesses at the bottom of gate trenches while maximizing the space to be filled with a low-resistance metal; using ALD minimizes the occurrence of preferential paths, at gate sidewalls, for Al diffusion into the high-k dielectric, reducing gate leakage (J G). For multi-gate fin field-effect transistors (FinFETs) which require smaller EWF shifts from mid-gap for low-V T: 1) conformal, lower-J G ALD-TiN/TaSiAl; and 2) Al-rich ALD-TiN by controlled Al diffusion from the fill-metal are demonstrated to be promising candidates. Comparable bias temperature instability (BTI), improved noise behavior, and slightly reduced equivalent oxide thickness (EOT) are measured on Al-rich EWF-metal stacks.

Biaxially-strained Ge p-channel field effect transistors (pFETs) have been fabricated for the first time in a 65 nm technology. The devices are designed to have a reduced effective oxide thickness (EOT) while maintaining minimized short channel effects. Low and high field transport has been studied by in-depth electrical characterization, showing a high hole-mobility that is enhanced by up to 70% in the strained devices. The important role of pocket implants in degrading the drive current is highlighted. Using a judicious implantation scheme, we demonstrate a significant gain in on-current (up to 35%) for nanoscaled strained Ge pFETs. Simultaneous optimization of the gate metal and dielectric, together with the corresponding uniaxial stress engineering, is identified as a promising path for further performance enhancement.

A dry-wet patterning process for La2O3/HfO2-containing high-κ/ metal gate stacks was successfully developed. The process meets the stringent requirements of complete removal of the high-κ layers and metal-containing sidewall residues without inducing silicon recess or undercut. The interaction between the dry etch and wet clean steps was studied. Use of a BCl3-based plasma process facilitated the cleaning process as it damages and modifies the high-κ layers in the active area. When the dry etch process ends with a BCl3-step, La-containing residues were formed inhomogeneously over the wafer within the time scale of hours. These residues could no longer be removed with a wet clean, but were not observed when the dry etch and wet clean processes were integrated. This demonstrates that an integrated etch-clean process enlarges the process window.