The present study reports the impact of process conditions and post annealing treatment on the stress and physico-chemical properties in different types of plasma enhanced atomic layer deposited (PEALD) SiNx films. More specifically, the SiNx films deposited at 500 °C were annealed subsequently at 1000 °C in N2 ambient for different times ranging between 30 and 6750 s and were subjected to thickness, mass, refractive index, chemical bonds and structure, H content, N/Si stoichiometry, morphology, roughness, and uniformity monitoring. Depending on the deposition process conditions, we confirm the possibility to form, at 500 °C with PEALD, some very compressive SiN films with reduced hydrogen content by controlling the plasma conditions along the deposition process. More interestingly, these compressive films with low hydrogen concentration exhibit high thermo-mechanical stability compared to hydrogenated PEALD and plasma enhanced chemical vapor deposition silicon nitride from this study or reported in the literature, films which typically tend to become tensile with a similar annealing sequence. These results confirm the importance of the plasma power to engineer the as-deposited silicon nitride stress but also highlight the role of hydrogen in the thermal instability of these layers, a low H concentration being needed for a better mechanical stability.

In this study, we explored the key properties and functionalities of plasma enhanced atomic layer deposition (PEALD) SiNx films, synthesized using different deposition temperatures (500–550 °C) and plasma conditions (lower and higher), both on 300 mm blanket Si and on several integrated 3D topology substrates, at the thicknesses relevant for diverse nanoscale applications. Our study shows that with an increase of temperature (500–550 °C), a small reduction in HF wet etch rate (1.1–0.69 nm/min), and H content (9.6% vs 7.4%) was observed. When using higher plasmas, significant improvements in blanket properties were observed. The films were denser (2.95 g/cm3), exhibited lower H content (2.4%), showed better etch rates (0.39 and 0.44 nm/s for HF and CF4 based), and SiNx grew without any nucleation delay on alternative Si1−xGex channel surfaces. The vertical and lateral conformality was found to be similar and appears not to be impacted with the plasma conditions. Extensive steam oxidation barrier studies performed at the sidewalls of different aspect ratio lines showed the PEALD SiNx liner scaling potentiality down to 1 nm when deposited using higher plasma. In addition, the outer gate and inner spacer properties were found to be superior (with lower loses) for higher plasma films when subjected to several dry etch, strips, and H3PO4 chemistries. The outstanding conformality (90%–95% on aspect ratios ≤10:1) combined with excellent high end material properties in the ultrathin regimes (1–10 nm) corroborate the virtue of PEALD SiNx toward integration in scaled down and advanced nanoelectronics device manufacturing.

Buried power rail (BPR) is a key scaling booster for CMOS extension beyond the 5-nm node. This work demonstrates, for the first time, the integration of tungsten (W) BPR lines with Si finFETs. BPR technology requires insertion of metal in the front-end-of-line (FEOL) stack. This poses risks of stack deformation and device degradation due to metal-induced stress and contamination. To assess the stack deformation, we demonstrate W-BPR lines which can withstand source/drain activation anneal at 1000 °C, 1.5 s, without adversely impacting the stack morphology. To address the contamination risk, we demonstrate a BPR process module with controlled W recess and void-free dielectric plug formation which keeps the W-line fully encapsulated during downstream FEOL processing. Suitable choice of BPR metal such as W with high melting point which does not diffuse into dielectrics also minimizes the risk of contamination. To assess the device degradation, simulations are carried out showing negligible stress transfer from BPR to the channel. This is experimentally validated when no systematic difference in the dc characteristics of CMOS without BPR versus those in close proximity to floating W-BPR lines is observed. Additionally, the resistance of the recessed W-BPR line is measured ~120 Ω/μm for critical dimension (CD) ~32 nm and height ~122 nm. The recessed W-BPR interface with Ru 3-nm TiN liner via contact can withstand more than 1000 h of electromigration (EM) stress at 6.6 MA/cm2 and 330 °C, making Ru a candidate for via metallization to achieve low resistance contact strategy to BPR.

In this paper, doping challenges are discussed for improvements of FinFETs and GAA FETs characteristics, and it is concluded that reduction of doping damage and conformal doping are technical solutions for the performance improvements.

Systematic experimental studies on phosphorus diffusion from phosphosilicate glass into the p-type bulk Si (100) substrate with different capping barrier layer thicknesses have been conducted. In both 2- and 5-nm phosphosilicate glass conditions, a thicker SiO2 cap showed a lower sheet resistance and a higher retained phosphorus dose in the Si substrate after 1050 °C 4 s rapid thermal annealing as drive-in annealing. However, the sheet resistance of 2-nm phosphosilicate glass with a 10-nm SiO2 cap was lower than that of 5-nm phosphosilicate glass with a 3-nm SiO2 cap due to a higher retained phosphorus dose in the Si substrate. For a higher retained phosphorus dose in the Si substrate using fixed total thickness, 2-nm phosphosilicate glass with 6-nm SiO2 cap is better than 5-nm phosphosilicate glass with 3-nm SiO2 cap since prevention of phosphorus out-diffusion during the drive-in annealing is more important than the total phosphorus dose in phosphosilicate glass. Next, SiO2 cap thickness on 2-nm phosphosilicate glass was split to understand the role of the SiO2 capping layer in detail for scaled devices. 3-nm SiO2 cap could not prevent out-diffusion during the drive-in annealing, and it showed much higher sheet resistance and lower retained phosphorus dose in the Si substrate. The highest retained phosphorus dose in the Si substrate was observed for 6-nm SiO2 cap and resulted in 1.8 × 1014 atoms/cm2 retained phosphorus dose with 96% activation level after 1050 °C 4 s rapid thermal annealing. Thicker SiO2 caps than 6 nm were not beneficial since 10-nm SiO2 cap showed a higher sheet resistance value as well as lower phosphorus activation level (82%) compared to 6-nm SiO2 cap even though both the process conditions showed same phosphorus profiles after the drive-in annealing. That sheet resistance increase with 10-nm SiO2 cap could be caused by heterogeneous surface formation on the Si substrate with a prolonged SiO2 atomic layer deposition process.

The solid state reaction of an ultra-thin Ni film (6nm) with Si:P epi layers (P: 0.7 to 4.0%), grown on 300-mm Si wafers, is studied as a function of different rapid thermal process (RTP) annealing temperatures (250–550°C) before and after applying a selective etch. The films are characterized using sheet resistance (Rs), mass, glancing incidence X-ray diffraction (GIXRD), X-ray reflectivity (XRR) atomic force, scanning electron and transmission electron microscopy (AFM, SEM and TEM) analyses to follow the onset of the Ni reaction, the evolution of the different phases formed within the Ni–Si system and to investigate the NiSi film properties. Results demonstrate that, though the Ni conversion to form an intermediate Ni-rich silicide phase is complete at 300°C, showing no dependency on the P content, the complete transformation (to form low resistive NiSi) shows a temperature dependence with P content (350°C vs 400°C for 0.7% P and 2.0–4.0% P). Despite the delay in silicidation completion, the NiSi films exhibit comparable layer properties, for all P contents. All films show a uniform conversion with a similar volume expansion (2.1), good interface properties, comparable resistivity (18–20μΩ·cm) and exhibit a smooth morphology with limited rms roughness increase (0.37 to 0.56nm). The thermal stability studies carried out on NiSi, post RTP anneals, shows a different Rs stability (650 and 575°C for 0.7% and 2.0–4.0% P), while the morphological and phase stability is found to be similar (≤500°C) for all P contents. The contact resistance measured using Circular Transmission Line Model (CTLM) structures for the synthesized NiSi films is found to be 4.8×10−8 and 1.2×10−8Ω·cm2 for 0.7% and 4.0% P respectively, the latter meeting the requirements for 10-nm CMOS technology node as predicted by International Technology Road Map for Semiconductors (ITRS).

The synthesis of nickel silicide thin films via a vapor-solid reaction has been studied by exposing thin (10 nm) Ni films to silane (SiH4). The crystalline phases, the Ni/Si stoichiometric ratios, as well as the surface and interface properties of the resulting silicide films were investigated as a function of the growth parameters such as the SiH4 partial pressure, the reaction temperature, and the exposure time. At low temperature (300 degrees C), SiH4 exposure led to the self-limiting deposition of Si on Ni by catalytic decomposition of SiH4 but not to silicate formation. Between 350 and 400 degrees C, phase pure orthorhombic NiSi films were obtained that were formed directly without any apparent intermediate Ni-rich silicide phases. A transformation to NiSi2 occurred at 450 degrees C and above, and at 500 degrees C phase pure NiSi2 was obtained. Here, the transient formation of NiSi was observed that transformed into NiSi2 for prolonged SiH4 exposure. The results indicate that the Si solubility governs the phase formation sequence whereas kinetics are determined by Ni diffusion and the reaction rate. Resistivity values of 21 and 36 mu Omega cm were found for the NiSi and NiSi2 thin films, respectively, corresponding to the values reported for films obtained by solid-state reactions.

The effective work function (EWF) and the energy position of the valence band in 20-40-nm thick VO2 and V2O5 layers grown by atomic layer deposition (ALD) on top of insulating SiO2 and gamma-Al2O3 films were evaluated using the comparison between capacitance-voltage and internal photoemission measurements. From the capacitance measured at different temperatures on the metalVO(2)( V2O5)-insulator-silicon and metal-insulator-silicon diodes we found that the both studied vanadium oxides have the same EWF as gold electrodes evaporated on the same oxides. This result is further collaborated by the internal photoemission experiments at the VO2/SiO2 and V2O5/SiO2 interfaces which indicate the energy barrier between the top of the vanadium oxide valence band (in the insulating phase) and the insulator conduction band to be 4.1 +/- 0.1 eV. Since the transition from the narrow-gap VO2 to the wide-gap V2O5 oxide causes no change in the WF or in the photoemission threshold, we conclude that the ALD-grown VO2 in its insulating phase represents a a heavily-doped semiconductor which becomes metallic upon metal-insulator transition without significant EWF change. (C) 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim

Nanoscale morphology of vanadium dioxide (VO2) films can be controlled to realize smooth ultrathin (<10 nm) crystalline films or nanoparticles with atomic layer deposition, opening doors to practical VO2 metal-insulator transition (MIT) nanoelectronics. The precursor combination, the valence of V, and the density for as-deposited VO2 films, as well as the postdeposition crystallization annealing conditions determine whether a continuous thin film or nanoparticle morphology is obtained. It is demonstrated that the films and particles possess both a structural and an electronic transition. The resistivity of ultrathin films changes by more than two orders of magnitude across the MIT, demonstrating their high quality.

The products of the solid state reaction involving ultra-thin Ni film (6nm) and Si1−xGex layers (Ge 25 and 55at.%), were analysed using sheet resistance (Rs), glancing angle X-ray diffraction (GIXRD), scanning electron and atomic force microscopy (SEM, AFM) techniques. The reaction was carried out via rapid thermal process (RTP) annealing using two different steps (RTP1 and RTP2) while applying a selective etch (SE) in between them. The intermediate and the end reaction products resulting after RTP1 and RTP2 were found to be dependent on the Ge content, forming Ni-rich silicide (Ni2Si) and NiSi on Si75Ge25, while Ni-rich germanide (Ni5Ge3) and NiGe were obtained by using Si45Ge55. Though the onset of intermediate Ni-rich silicide or germanide phase formation occurs at similar RTP1 temperature (275°C), the reaction completion to yield low resistive phase NiSi or NiGe phase results at different RTP2 temperatures (400°C vs 350°C). Based on the volume expansion, a resistivity value of 25μΩcm was obtained for the synthesized NiGe (12nm) and NiSi (14nm) layers. Independent of the phases obtained, the films were found to be closed and homogeneous and exhibit rms roughness of 0.5–0.8nm as evidenced by SEM and AFM analysis. Thermal stability studies carried out on NiSi and NiGe thin films, post RTP1/RTP2, show the latter phase to have limited stability and result in Rs degradation starting already at 475°C due to phase decomposition.

We discuss the selection criteria for alternative metals in order to fulfill the requirements necessary for interconnects at half pitch values below 10 nm. The performance of scaled interconnects using transition metal germanides and CoAl alloys as metallization are studied and compared to conventional Cu and W interconnects.

Crystalline vanadium dioxide (VO2) thin films were prepared by annealing amorphous VO2 films which were deposited by atomic layer deposition on a SiO2 substrate. A large influence of the oxygen partial pressure in the annealing ambient was observed by means of in-situ X-ray diffraction. In the range between 1 and 10Pa of oxygen the interesting VO2(R) phase crystallized near 450°C. Between 2 and 10Pa of oxygen, metastable VO2(B) was observed as an intermediate crystalline phase before it transformed to VO2(R). Anneals in inert gas did not show any crystallization, while oxygen partial pressures above 10Pa resulted in oxidation into the higher oxide phase V6O13. Film thickness did not have much effect on the crystallization behavior, but thinner films suffered more from agglomeration during the high-temperature crystallization on the SiO2 substrate. Nevertheless, continuous polycrystalline VO2(R) films were obtained with thicknesses down to 11nm. In the case where VO2(R) was formed, the semiconductor–metal transition was observed by three complementary techniques. This transition near 68°C was characterized by X-ray diffraction, showing the transformation of the crystal structure, by spectroscopic ellipsometry, mapping optical changes, and by sheet resistance measurements, showing resistance changes larger than 2 orders of magnitude between the low-temperature semiconducting state and the high-temperature metallic state.

With the downscaling of the interconnect technology, the resistance of industry standard Cu increases for the sub-20 lines due to the increased grain boundary and surface scattering. With the reduction of the geometry sizes and increase of aspect ratios, the ability to achieve a uniform Cu metallization becomes challenging. Hence, interests on low resistive alternative metals or alloy thin films deposited with good trench filling capability technologies becomes increasingly important. In this context, in the present study, an unconventional route is explored to synthesize Cu3Ge films via CVD of GeH4 gas with thin solid Cu films at BEOL compatible temperatures (250 degrees C). Results show that epsilon(1)-Cu3Ge films could be successfully grown on 300 mm blanket and on patterned wafers by exposing GeH4 precursors over Cu films at 250 degrees C. The GeH4 CVD conditions were optimized, on different thicknesses of Cu, to grow phase pure and stoichiometric low resistive Cu3Ge layers on blanket wafers. In-situ XRD analyses combined with anneal studies show that the Cu3Ge films are thermally stable up to 600 degrees C with no signs of decomposition. Our investigation was further extended to the growth of Cu3Ge in trenches and showed that the GeH4 decomposition-cum-reaction with Cu is uniform along the trench depth, completely transforming the Cu to Cu3Ge films with a limited volume expansion, as evidenced by the GIXRD, SEM and TEM analysis. (C) 2013 Elsevier B.V. All rights reserved.

A low temperature process, relying on the catalytic chemical vapor reaction of GeH4 with solid Co layers, is developed to synthesize ultra-thin CoGe2 layers (10-20 nm) on 300 mm Si wafers. The selective reaction of Co with GeH4 results in the direct formation of CoGe2 films crystallizing in the orthorhombic structure. Detailed studies under germanidation reaction conditions show that the optimal temperature (325 degrees C vs. 400 degrees C) to obtain low resistive, defect free and continuous CoGe2 films depends on the initial Co thickness. Investigation on various stages of cobalt germanide growth evolution demonstrates that the complete conversion of Co, leading to closed and stoichiometric CoGe2 films, occurs after 60 s of GeH4 exposure as evidenced by atomic force microscopy (AFM), Rutherford back scattering (RBS) and sheet resistance (R-s) analysis. The CoGe2 formation is found to exhibit self-limiting growth. The layers demonstrate constant film properties (phase purity, resistivity, composition homogeneity, uniformity, and smooth morphology with insignificant rms roughness increase) within a large process window, negligibly influenced by excessive GeH4 exposure conditions. Independent of the post-deposition annealing employed (RTA or furnace annealing), results showed the CoGe2 layers to be thermally stable up to 500 degrees C without phase or morphological degradation or film roughening. Resistivity values in the range of 70-50 mu Omega cm were observed for 10-20 nm CoGe2 films.

The SiOxCyHz layers synthesized by means of the atmospheric pressure glow-like DBD assisted PECVD technology show remarkable planarizing film properties, observed for the first time. The films were deposited in a roll-to-roll mode on large area polymeric webs using HMDSO and air as the precursor and oxidiser. FTIR analysis show the carbon content in the SiOx films is strongly correlated with the precursor flow rate resulting in SiO2-like layers with negligible carbon content at lower flow values (0.4g/h), while at higher flow rates carbon rich SiOxCyHz films were obtained. Detailed AFM surface profile analysis show that the SiOxCyHz films smoothen out the global and local surface structures of the polymer comprising a reduction in rms surface roughness (0.99 +/- 0.11nm) and increase of roughness exponent (=0.97 +/- 0.02) compared to that of PEN polymer. These ultra-smooth organic layers together with the smooth inorganic SiOx layers (1.75 +/- 0.12nm), exhibiting roughness comparable to the polymer (1.50 +/- 0.07nm) at lower precursor input, provide an efficient route to fabricate multilayer hybrid structures in a single chamber synthesis.