This work demonstrates a novel energy-efficient tunnel FET (TFET)-CMOS hybrid foundry platform for ultralow-power AIoT applications. By utilizing the proposed monolithic integration process, the novel complementary n and p-type Si TFET technology with dopant segregated source junction and self-aligned drain underlap design is successfully integrated into a 300mm CMOS baseline process without CMOS performance penalty and any new materials, experimentally demonstrating the large Ion and record high Ion/Ioff ratio of 10^7 among TFETs by industry-manufacturers. The device performance and variability are also co-optimized for high-volume production. Further circuit-level implementations are presented based on the calibrated compact model. The proposed TFET-CMOS hybrid logic and SRAM topologies show significant energy efficiency improvement with comparable operation speed compared with standard CMOS circuits, indicating its great potential for power-constraint AIoT applications.

Tunnel Field Effect Transistor (TFET) which has a subthreshold swing lower than 60mV/decade and ultra-low off-current has become one of the most promising candidates to replace MOSFET in ultra-low-power applications, such as artificial intelligence of things. In this paper, we study the TFET-based static random access memory (SRAM) design and propose a novel 8T TFET-MOSFET hybrid SRAM based on the compact model of recently manufactured TFET in 12-inch foundry platform. The proposed design uses a single MOSFET as the write access transistor and the TFET-MOSFET stacked structure as the read access transistor which eliminates the forward p-i-n current fundamentally. Compared with 6T CMOS SRAM, the proposed design demonstrates 3 orders of magnitude lower static and read power, and 6 orders lower write power. Besides, it achieves faster read and write speed than other reported TFET SRAM designs. It also has the maximum hold, read and write static noise margin among all the CMOS and TFET SRAM designs.

This paper proposed a nano-watt voltage reference circuit was implemented in a 0.18um CMOS process with trim techniques. In order to reduce power consumption, a MOS-Only Voltage Reference is presented, which is based on the threshold voltage, However, the deviation of Vref because of process variation is large. We use the difference of Vth instead of Vth to improve the stability of output voltage at different process corner. The simulation results show that under 27°C and 0.5V supply voltage, the output reference voltage is 236mV, the temperature coefficient is 30.8 ppm/°C over temperature range of 125°C (-40°C to 85°C) and only consume 5.5nW at 0.5V supply voltage.

Tunnel FET (TFET) is recognized to be one of the most promising candidates for ultra-low power applications due to its ultra-low off current and high compatibility with CMOS process. However, different from the typical features of MOSFET, some electrical characteristics of TFETs caused by asymmetric device structure and special conduction mechanism may make conventional topologies of circuits no longer applicable. In this paper, it is found that the TFETs stacking will result in severe current degradation behavior, which makes traditional topologies of logic gates may be not applicable. To solve this problem, a set of novel hybrid TFET-MOSFET topologies for standard logic cells are proposed. The proposed designs achieve more than 2 times lower hardware cost and intrinsic delay, and realize up to 4 times lower area-power-delay product (APDP) than that of conventional TFET-based logic circuits. Moreover, the proposed topologies can achieve almost 2 orders of magnitude lower power and up to 34 times lower APDP than that of conventional MOSFET-based logic circuits. The proposed standard logic cells show great superiority for power-constraint applications.

This paper proposed a 0.9-to-1.2V output voltage boost DC-DC regulator for wireless energy harvesting of which the power efficiency has been much improved under light load condition utilizing pseudo open loop structure (POLS) and power efficient ring oscillator. The POLS makes the whole system work in the open loop state when the output voltage is stable, so the energy cost for voltage regulating can be saved a lot. The POLS is realized by two hysteresis comparators controlled by a very slow clock, the comparators generate different threshold voltage by a single reference and those different thresholds can lock up the output. The power efficient ring oscillator generates the feedback control frequency ranges from 230Hz-to-220KHz utilizing an 11-bits-binary series capacitor array. Accordingly, a boost DC-DC, which operates in discontinuous-conduction mode (DCM) and regulates voltage by a constant-on-time pulse frequency modulation (PFM), is proposed. As a simulation result, the input voltage ranges from 0.3-to-0.5V and the output voltage ranges from 0.9-to-1.2V while the output load ranges from 1μw-to-100μw, the peak efficiency is 83.7% when the load is 1μw.

In this paper, a novel combinational access topology of Tunnel FET (TFET) SRAM is proposed for ultra-Low Power applications. Since forward p-i-n current of TFET could cause serious damage to SRAM circuit performance, the proposed topology can avoid the forward bias applied to the p-i-n junction, thus increasing SRAM cell read and hold static noise margin (SNM) and decreasing its static power consumption dramatically. At 0.6 V supply voltage, the combinational access TFET SRAM topology presents 26% hold SNM larger than traditional TFET SRAM topologies, 8 orders of magnitude lower static power consumption, and 2 order of magnitude lower power delay product, demonstrating its great potential for ultra-low power applications.

In this work, the power, performance and area of novel multi-Finger Schottky-Barrier Tunnel FET (mFSB-TFET) are benchmarked with standard MOSFET and low-power MOSFET from device and circuit level. Under the same area penalty, mFSB-TFET circuits could obtain comparable delay with significantly lower static and total power consumption by orders of magnitude than standard MOSFET circuits. The advantages are more significant at ultra-low working voltage, even compared with low-power MOSFET circuits, indicating great practical potential of mFSB-TFET for ultra-low power application.

Low power applications have led to a boom in researches on new circuits based on steep-slope transistors, of which the objective is to overcome MOSFET's drawback of inevitable increasing leakage power while maintaining acceptable performance in low voltage operation. Among those emerging transistors, Tunnel FET (TFET) becomes a most promising one due to its low off current and compatibility with CMOS process. In order to guide the application and the improvement of TFET, in this paper from a circuit-level perspective, utilizing a newly defined benchmarking method, we figured out the frequency-VDD range in which Si TFET circuits show low power advantage over their MOSFET counterparts based on HSPICE simulations using calibrated compact model. A systematic and quantitative analysis was then conducted to further enlarge the application scope of TFET circuits, with a Figure of Merit (FOM) and a guideline for future TFET proposed.

A continuous surface-field-based compact model for heavily doped junctionless nanowire transistors is developed. By constructing specific transformation variables, an algebraic relation between the surface field and potential is identified to facilitate a computationally efficient model for calculating the (long-channel) drain current from the oxide-interface boundary condition with no need of the surface-potential approach. The model accuracy at high doping levels is further improved by incorporating a second-order correction. A short-channel-effect model is also developed using the eigenfunction-expansion method to solve the 2-D Poisson's equation. A good agreement between the model prediction and TCAD simulations is observed. Finally, high model accuracy is verified by the experimental data.

A nonlinear surface-field-based model for heavily doped JL nanowire MOSFETs is developed. By introducing two specific transformation variables, the surface potential to the field (due to the mobile charge) are correlated by a simple algebraic relation. Without solving the electrostatic potential, a drain current model is derived by the Pao-Sah integral. A second-order correction is carried out to improve the model accuracy.

For the first time, an analytic surface-field-based model for nanowire MOSFETs with random dopant fluctuations (RDF) is reported. In this model, the depletion charge due to the discrete dopant distribution is described by the Dirac δ functions, while the mobile charge keeps its continuous form. By introducing two new variables, the discrete 1-D Poisson's equation is transformed into a simple algebraic equation to correlate the surface potential with the field (due to the inversion charge). Without solving the potential distribution, the drain current can be calculated from the Pao-Sah integral using the oxide-interface boundary condition. This model is shown to be more accurate in predicting the RDF effects than the continuous TCAD simulations for all the operating regions. We also discuss the RDF-incorporated short-channel effects by solving the discrete 2-D Poisson's equation in the subthreshold regime.

In this work, the impacts of electrical characteristics of Tunnel FET (TFET) on the SRAM design are systemically investigated for the first time from the perspective of memory array. A novel 10T TFET SRAM design is also proposed to overcome the challenges and improve the circuit stability. By using a calibrated compact model, the simulated static power of 10T TFET SRAM can be much lower than traditional 6T MOSFET SRAM, especially at the low supply voltage of 0.5V. In addition, the cell's stability is also largely improved with the largest noise margin compared with reported 7T TFET SRAM design and traditional 6T MOSFET SRAM.

Photoelectrodes using different nanoparticle size and film thickness of TiO2 were prepared by screen-printing and post annealing method with the objective of optimizing the photovoltaic performance of dye-sensitized solar cells (DSSCs). The effect of nanoparticle size and film thickness of the TiO2 on the performance of DSSCs was investigated. Based on the effect investigation, composite nanoparticulate TiO2 film electrodes were designed and fabricated to improve the photovoltaic performance of the DSSCs. The enhanced conversion efficiency was achieved in the DSSCs by introducing light scattering layer and additional dye adsorption nanoparticle layer to form composite TiO2 films, and by optimizing the nanoparticle size and film thickness. The improvement mechanism was also discussed.

TiO2-based resistive switching memory devices with an inserted ZnO layer were fabricated, and the effect of inserting a ZnO layer between the TiO2 and bottom electrode on the reliability characteristics of TiO2-based memory devices was investigated. The improved endurance and retention performances were achieved in the TiO2-based memory device fabricated with an inserted ZnO layer. The mechanism of reliability improvement was discussed. The inserted ZnO layer is proposed to adjust the distribution of oxygen vacancies across the TiO2 layer due to the lower formation energy of oxygen vacancy in ZnO, which may be responsible for the improved reliability characteristics in the TiO2-based memory device with an inserted ZnO layer.

The self-diffusion model of Lennard-Jones fluid confined in a nanoscale space is developed by using equilibrium molecular dynamics simulation. The radial distribution function in free and confined space is evaluated and compared to analyze the fluid microstructure. The effects of the confined scale, strength of the fluid–solid coupling and commensurability of wall and fluid density on the fluid self-diffusion are investigated and discussed. The results indicate that the confined scale, fluid–solid coupling strength and commensurability of wall and fluid density play considerable role in the self-diffusion coefficient for the fluid confined in nanoscale space. Decrease in the confined scale lead to large portion of fluid molecules ‘feel’ the wall interaction, which results in the reduction of self-diffusion coefficient. In addition, the reduction of fluid self-diffusion coefficient in confined space is also demonstrated when the wall and fluid densities are incommensurate and wall–fluid coupling strength is large.

A self-diffusion model of Lennard-Jones (LJ) fluid in confined space was developed by using equilibrium molecular dynamics (EMD) simulation method. The radial distribution function is utilized to analyze the LJ fluid microstructure. The self-diffusion coefficient of LJ fluid in the nanoscale confined space is calculated and compared with that in free space. The effects of temperature, density, and confined scale on the self-diffusion coefficient are all investigated and discussed at the molecular level. The results indicate that the LJ fluid self-diffusion coefficient in confined space increases with the increasing confined scale. Similar to that in free space, the LJ fluid self-diffusion coefficient in confined space also increases approximately in a linear fashion with temperature, while it decreases gradually with the increasing density. However, the LJ fluid self-diffusion coefficient in confined space is smaller than that in free space with the same temperature and density. In addition, the accuracy of the self-diffusion coefficient calculated by the present model is verified by the experimental data available in the literature.

The fermentation of non-starch polysaccharides by colonic microflora is popular as a triggering mechanism to achieve colon-specific drug delivery in that the existence of colonic microflora is independent of gastrointestinal transit time, pH, and disease conditions, and various delivery systems were developed using this strategy. One of such delivery systems, COLAL technology, has advanced into late stage of product development. However, in vitro characterization of these delivery systems remains a challenge in part because the critical performance indicator is colonic specificity of drug release. Moreover, the dynamic and ecologically diverse features of the colon are difficult to be incorporated into USP dissolution methods. As a result, alternative dissolution approaches have been designed to better represent the colonic conditions, such as utilizing polysaccharide-degrading enzymes, rat caecal contents, human fecal slurries, and multi-stage culture systems. The primary focus of this article is to summarize and review the dissolution testing currently used in characterizing colon-specific delivery systems activated by microflora. A brief description of physiological parameters of the colon relevant to colonic drug release is also presented.

In an H.264 video encoder, motion estimation (ME) is the most time-consuming component. The ME process consists of two stages, integer pixel search and fractional pixel search. Since the complexity of integer pixel search has been greatly reduced by numerous fast ME algorithms, the computation overhead required by fractional pixel ME has become relatively significant. To reduce the complexity of fractional pixel ME, we propose a prediction-based directional fractional pixel ME algorithm. We utilize more accurate motion vector predictions and directional search to achieve better computation reduction. We further propose an early termination method to decrease the amount of search. Experimental results show that, compared to the full search sub-pel ME and the fast sub-pel ME proposed in H.264, the proposed method can reduce up to 84% and 74% of fractional pixel search points respectively, with a negligible degradation in quality.

The H.264 video coding standard provides considerably higher coding efficiency than previous standards do, whereas its complexity is significantly increased at the same time. In an H.264 encoder, the most time-consuming component is variable block-size motion estimation. To reduce the complexity of motion estimation, an early termination algorithm is proposed in this paper. It predicts the best motion vector by examining only one search point. With the proposed method, some of the motion searches can be stopped early, and then a large number of search points can be skipped. The proposed method can work with any fast motion estimation algorithm. Experiments are carried out with a fast motion estimation algorithm that has been adopted by H.264. Results show that significant complexity reduction is achieved while the degradation in video quality is negligible.

This paper presents a sampling-based approach to computing and executing feedback-motion strategies by defining a global navigation function over a collection of neighborhoods in configuration space. The collection of neighborhoods and their underlying connectivity structure are captured by a sampling-based neighborhood graph (SNG), on which navigation functions are built. The SNG construction algorithm incrementally places new neighborhoods in the configuration space, using distance information provided by existing collision-detection algorithms. A termination condition indicates the probability that a specified fraction of the space is covered. Our implementation illustrates the approach for rigid and articulated bodies with up to six-dimensional configuration spaces. Even over such spaces, rapid online responses to unpredictable configuration changes can be made in a few microseconds on standard PC hardware. Furthermore, if the goal is changed, an updated navigation function can be quickly computed without performing additional collision checking.