This work describes for the first time, RFIC stacked at the top-tier of a 3D sequential integration. The analog silicon RF circuits, sequentially fabricated at 500°C above a digital circuit layer with 28nm FDSOI industrial platform, present performance in line with standard thermal budget FDSOI devices. Thanks to this advanced 3DSI stack, top-tier VCO and LNA functional demonstrators are designed in the 30 GHz band. Additionally, a signal integrity study is carried out using a ring oscillator aggressor, integrated on bottom-tier below the VCO core, highlighting the interoperability of an aggressive vertical co-integration between fast digital and RF blocks. This work provides insights into the crosstalk issue arising from the ultra-thin distance between tiers, a characteristic feature of3DSI.

This paper evaluates the lateral dopant diffusion for source and drain junction profiles of NMOS FDSOI devices. Parameters of the phosphorus diffusion model in an in-situ doped epitaxial Source/drain are calibrated using TCAD simulations, and validated against experimental data, which vary with spike anneal temperatures, epitaxy concentrations, and gate lengths. After carefully adjusting these parameters, we incorporate them into a global simulation approach for device scaling. This enables the transition from current baseline FDSOI technology to even advanced FDSOI technology nodes.

This work demonstrates for the first time the 3D sequential integration of CMOS over CMOS with advanced metal line levels (28nm Cu + ULK). The bottom tier consists of a 28nm FDSOI industrial wafer with 4 metal lines. A bevel contamination wrap module allows the return of the wafer to Front End Of Line (FEOL) environment required for achieving high performance top FET Si CMOS processing. Additionally the doped poly-Si ground plane introduced enables top FET dynamic back-biasing and effective DC and HF isolation with underlying metal lines. Finally, this 3DSI platform demonstrates functional top, bottom, and 3D ring oscillators as well as a pixel with single exposure flicker-free High Dynamic Range capability obtained thanks to the stacking of an additional circuit over a bottom 3T-pixel.

We present, for the first time, a new CV based technique to extract the Active Dopant Profile under the spacer in thin film FDSOI devices (CV-AJP). The methodology is successfully applied to FDSOI devices fabricated at 500°C for 3D sequential integration. It shows that the ION/ IOFF trade-off relies mainly on the chemical dopant introduction below the offset spacer, as the activation level obtained with thermal activation is found to be high enough. The LT device demonstrated in this work, already outperforms the literature. The active profile extraction also allows to draw guidelines for further device performance improvement: using a scaled SiCO spacer (5,5nm) allows to circumvent the negligible dopant diffusion at 500°C without dynamic performance penalty due to its low-k dielectric value.

This paper investigates silicon oxide bevel deposition to manage contamination in 3D integration with intermediate BEOL levels. Films are deposited on the bevel area of 300 mm wafers thanks to a torus shaped PECVD configuration allowing encapsulation of the last few mm of the wafer frontside, backside and the apex in a single processing step. Deposition is carried out at 350 °C from mixture of SiH4 and N2O at 2 torr. When the gap between wafer and top insulator increases from 0.4 to 0.7 mm, the frontside deposition profile is shifted by 0.5 mm inward. In accordance with refractive index of 1.55 measured by ellipsometry, surface analysis by XPS show a film composition of SiO1.8N0.3 with a quasi-constant composition from 147 to 149 mm wafer radius. The film resistance, evaluated by wet etch in 2% HF, leads to wet etch rate ratio to thermal oxide of 4-5. We demonstrate that such films are compatible with oxide bonding. Thanks to a proper integration scheme, minimal impact on the bonding edge quality with bonding limit of 147.7 mm on real product CMOS+M4 is reported. Finally, the effectiveness of the strategy to keep the metallic contamination at 1 x 1010 at.cm-2 or below is verified by either specific LPD bevel-ICPMS on BEOL wafers or by VPD-ICPMS standard process control on FEOL wet tool just after having cleaned BEOL wafers.

This paper investigates silicon oxide bevel deposition to manage contamination in 3D integration with intermediate Back-End Of Lines (iBEOL) levels. Bevel etching and cleaning techniques are now sufficiently mature to remove efficiently contamination on wafer bevel area. However, 3D integration with iBEOL could require encapsulating metal lines, which emerge on the bevel area. This paper explores the efficiency of bevel deposition to answer contamination issues in 3D integration. Films are deposited on the bevel area of 300 mm wafers thanks to a torus shaped Plasma Enhanced Chemical Vapor Deposition (PECVD) configuration allowing encapsulation of the last few mm of the wafer frontside, backside and the apex in a single processing step. Deposition is carried out at 350 °C from mixture of SiH 4 and N 2 O at 2 Torr. When the gap between wafer and top insulator increases from 0.4 to 0.7 mm, the frontside deposition profile is shifted by 0.5 mm inward. In accordance with refractive index of 1.55 measured by ellipsometry, surface analysis by X-ray Photoelectrons Spectroscopy (XPS) show a film composition of SiO 1.8 N 0.3 with a quasi-constant composition from 147 to 149 mm wafer radius. The film resistance, evaluated by wet etch in 2% HF, leads to Wet Etch Rate (WER) ratio to thermal oxide of 4–5. We demonstrate that such films are compatible with oxide bonding. Thanks to a proper integration scheme, minimal impact on the bonding edge quality with bonding limit of 147.7 mm on real product Complementary Metal Oxide Semiconductor with 4 Metal levels (CMOS+M4) is reported. Finally, the effectiveness of the strategy to keep the metallic contamination at 1 × 10 10 at.cm- 2 or below is verified by either specific Liquid Phase Decomposition bevel Inductively Coupled Plasma Mass Spectrometry (LPD bevel-ICPMS) on BEOL wafers or by Vapor Phase Decomposition (VPD)-ICPMS standard process control on Front-End Of Line (FEOL) wet tool just after having cleaned BEOL wafers. Display Omitted • 3D integration requires innovative strategies to process stacked wafers. • Wafer bevel deposition offers a solution to keep metal contamination compatible with front end of line tools. • The bevel management is compatible with wafer bonding and thinning.

In this article a review of low temperature (LT) (≤500 °C) process modules in view of 3-D sequential integration is presented. First, both the bottom device thermal stability and intermediate back end of line (iBEOL) versus thermal anneal and ns-laser anneal is determined, setting up the top device temperature fabrication process at 500 °C during a couple of hours. Then, the full LT process flow with process modules developed at 500 °C is exposed. Great progress and breakthrough for high performance (HP) digital stacked FETs has been made recently. Areas previously considered as potential showstoppers have been overcome: 1) efficient contamination containment for wafers with Cu/ultra low- ${k}$ (ULK) iBEOL enabling their reintroduction in front end of line (FEOL) for top FET processing; 2) low-resistance poly-Si gate for the top FETs and solutions for improving gate-stack reliability; and 3) full LT raised source drain (RSD) epitaxy including surface preparation combined with SiCO 400 °C spacer and SPER junctions activation. Finally, the first functional nMOS and pMOS demonstration with a 500 °C thermal budget (TB) is highlighted.

The aim of this paper is to present the 3D-sequential integration and its main prospective application sectors. The presentation will also give a synoptic view of all the key enabling process steps required to build high performance Si CMOS integrated by 3D-sequential with thermal budget preserving the integrity of active devices and interconnects and will sketch a status and prospect on current low temperature device performance.

In this article a review of low temperature (LT) (≤500 °C) process modules in view of 3-D sequential integration is presented. First, both the bottom device thermal stability and intermediate back end of line (iBEOL) versus thermal anneal and ns-laser anneal is determined, setting up the top device temperature fabrication process at 500 °C during a couple of hours. Then, the full LT process flow w...

3D sequential integration (3DSI) is envisioned for highly miniaturized smart imagers and fine pitch logic and memory imbrication. This paper describes partitioning in 3DSI and design methodologies. A status is also done on low temperature processes and device performance adapted for these applications (i.e. digital $\mathrm{V}_{\text{DD}}\leq 1\mathrm{V}$ and analog $\mathrm{V}_{\text{DD}}\geq 2.5\mathrm{V}$ devices).

For the first time FDSOI CMOS transistors with Si-monocrystalline channel have been fabricated at a temperature below 500°C. High performance PMOS (Ion=450μA/μm (Vdd −0.9V) @ Ioff=2nA/μm Lg=35nm) with low overlap capacitance (0.46fF/μm per device), low gate resistance (10Ω) at Low Temperature (LT) enables to achieve good RF Figure-Of-Merit (FOM) with Fmax values up to 170GHz. In addition, we demonstrate for the first time the full functionality of Ring Oscillators (RO) and SRAM bitcells processed at 500°C, paving the way for a high-performance 3D sequential CMOS integration.

BACKGROUND:RAS and K601E BRAF mutations are not a reliable indicator of malignancy in fine-needle aspirations (FNA) of thyroid indeterminate cytologic nodules. We aimed to evaluate the histologic characteristics, the risk of malignancy associated with such mutations in FNA and their potential interest for preoperative clinical management of nodules.METHODS:We evaluated 69 indeterminate thyroid nodules with RAS or K601E BRAF mutations with available histopathologic follow-up. All FNA specimens were indeterminate according to the thyroid Bethesda system. Diagnosis of malignant, benign or indolent neoplasms was classified according to 2017 WHO classification. Carcinoma, NIFTP (noninvasive follicular thyroid neoplasm with papillary-like features) and WDTUMP (well-differentiated tumor of uncertain malignant potential) were considered "surgical," as they require surgical excision. Adenoma was considered "non-surgical." The risk of malignancy and the risk of "surgical disease" were evaluated.RESULTS:Pathologic evaluation of the 69 mutated nodules demonstrated benign, indolent and malignant histology in 17 cases (25%), 21 cases (30%) and 31 cases (45%), respectively. The risk of malignancy was 45%, and the risk of surgical disease was 75%. The majority of carcinomas were a follicular variant of papillary thyroid carcinoma. On follow-up, there have been no recurrences to date.CONCLUSION:Preoperative RAS or BRAF K601E mutations detection in cytologic indeterminate thyroid nodules carries a high risk of surgical disease and may benefit from surgical management. Most surgical lesions harboring those mutations are low-risk tumors, which may be in favor of an initial lobectomy.

Gate-all-around (GAA) silicon (Si) nanowires (NW) field effect transistor is today considered as a valuable alternative to FinFET architecture for advanced CMOS devices. Recent advances in characterization and integration have enabled the fabrication of nanowires with diameter below 10 nm. Although nanowires transistors with excellent electrostatic control can be achieved, the nanoscale dimensions induce quantum confinement effects and confer to nanowires electrical properties which differ from bulk Si. Then, low-field electron and hole mobility in Si NW transistors fabricated on (100) silicon-on-insulator (SoI) substrates have been measured over a wide range of NW width (8 nm ≤ W ≤ 220 nm) and height (6 nm ≤ Hfin ≤ 24 nm). A significant increase of hole effective mobility in thick and narrow Si NWs is evidenced along the [110] direction. In contrast, a decrease of NW width results in an electron mobility reduction. An electron mobility enhancement in n-FET NWs is achieved through the use of tensile strained-SoI (sSoI) substrates. As compared to unstrained-Si, +85% electron mobility enhancement is observed in uniaxially tensile strained-Si NW transistors. We have otherwise studied dual-channel CMOS co-integration, with Si channel n-FET and compressively-strained SiGe channel p-FET NWs. For p-FETs, the efficiency of compressive SiGe channels is evidenced for improving hole mobility in nanowires thanks to a Ge enrichment process. As compared to Si channel, the hole mobility is enhanced by 135% in p-FET NWs. Efficiency of compressive SiGe channel is evidenced for ultra-scaled p-FET NWs (LG = 15 nm) with +90% ION current improvement compared to Si. [110]-oriented NWs are shown to be the best candidates to improve electron and hole mobility under uniaxial tensile and compressive strain, respectively. Finally, in order to increase still further the drive current per layout footprint, GAA stacked-nanowire/nanosheet (NS) MOSFET are discussed in this paper. We will present intrinsic performance and design considerations of GAA structures that will allow to make this architecture a competitive solution for futures technology nodes. The key technological challenges (such as 3D integration process including inner spacer and strain engineering) will be discussed in relation to recent research results. We will show that more flexibility can be achieved with stacked-nanosheet transistors in order to manage power and performance optimization.

Context. Within the framework of the second-generation instrumentation of the Very Large Telescope Interferometer of the European Southern Observatory we have developed the four-telescope beam combiner in integrated optics. Aims. We optimized the performance of such beam combiners, for the first time in the near-infrared K band, for the GRAVITY instrument dedicated to the study of the close environment of the galactic centre black hole by precision narrow-angle astrometry and interferometric imaging. Methods. We optimized the design of the integrated optics chip and the manufacturing technology as well, to fulfil the very demanding throughput specification. We also designed an integrated optics assembly able to operate at 200 K in the GRAVITY cryostat to reduce thermal emission. Results. We manufactured about 50 beam combiners by silica-on-silicon etching technology. We glued the best combiners to single-mode fluoride fibre arrays that inject the VLTI light into the integrated optics beam combiners. The final integrated optics assemblies have been fully characterized in the laboratory and through on-site calibrations: their global throughput over the K band is higher than 55% and the instrumental contrast reaches more than 95% in polarized light, which is well within the GRAVITY specifications. Conclusions. While integrated optics technology is known to be mature enough to provide efficient and reliable beam combiners for astronomical interferometry in the H band, we managed to successfully extend it to the longest wavelengths of the K band and to manufacture the most complex integrated optics beam combiner in this specific spectral band.

For the first time, a comprehensive study going from the integration of 3D stacked nanosheets Gate-All-Around (GAA) MOSFET devices to SPICE modeling is proposed. Devices have been successfully fabricated on SOI substrates using a replacement high- $\kappa$ metal gate process and self-aligned-contacts. Back-biasing is herein efficiently used to highlight a drastic improvement of electrostatics in the upper GAA Si channels. Advanced electrical characterization of these devices enabled us to calibrate a new version of physical compact model (LETI-NSP) in order to assess the performance of ring oscillators for different configurations of GAA FETs integrating up to 8 vertically stacked Si channels.

Les adénomes corticotropes expriment de manière variable le récepteur de la somatostatine de type 5 (STTR5) qui est une cible du PASIREOTIDE, traitement médical de la maladie de Cushing.

2018 International Conference on Solid State Devices and Materials,Introducing a highly efficient stressor for pMOS devices by controlling epitaxy and Ge enrichment in advanced planar FDSOI CMOS technology

This paper presents recent progress on Gate-All-Around (GAA) stacked-NanoWire (NW) / NanoSheet (NS) MOSFETs. Key technological challenges will be discussed and recent research results presented. Width-dependent carrier mobility in Si NW/NS and FinFET will be analyzed, and intrinsic performance and design considerations of GAA structures will be discussed and compared to FinFET devices with a focus on electrostatics, parasitic capacitances and different layout options. The results show that more flexibility can be achieved with stacked-NS transistors in order to manage power-performance optimization.