Recently Silicon Photonics has generated an outstanding interest for integrated optical communications. In this paper we describe a 300mm Silicon Photonics platform designed for 25Gb/s and above applications at the three typical communication wavelengths and compatible with 3D integration. Main process features and device results are described.

This paper describes realization and characterization of SrTiO3 (STO) high K MIM capacitors above BiCMOS integrated circuit (IC). These capacitances are connected to IC and are used as coupling capacitors in order to realize a high pass filter. Surface capacitance achieved is 10nF/mm2 with capacitance value of 1.2nF. The process for STO MIM fabrication does not exceed 400°C, which is compatible with interconnections. Typical K and dielectric losses values obtained are, respectively 110% and 2%. Yield obtained reaches 83% for capacitors. A functional high pass filter using these STO capacitors was realized in this study. It exhibits a cut-off frequency at 6.5kHz and a constant gain at higher frequencies of −1.3dB.

This paper summarizes the electrical characterization of MIM capacitor realized in three dimensions. Manufacturing of the device is described, as well as an electrical comparison of three dielectrics, Si(3)N(4), Al(2)O(3), Ta(2)O(5) and two deposition methods, metal organic chemical vapor deposition (MOCVD) and atomic layer deposition (ALD). Selecting Al(2)O(3) deposited by ALD, high density of 35 nF/mm(2) is obtained with low leakage current. Statistical measurements put forward the industrial robustness of the device integrated in BiCMOS technology. Three circuits embedding this new device are characterized: a high-pass filter, a voltage-controlled oscillator (WO), and a phase-locked loop (PLL). They demonstrate excellent performances with significant area and assembly costs savings.

Electrical Wafer Sort process is known to induce stress in the pad structure and can lead to yield loss. In the present paper, probing simulation with Finite Element Method is performed and faced to experimental measurements. Firstly, the contact surface for planar and non-planar impacts and the needle structural lateral reaction force studies are carried out with static simulation. Then, using explicit solver, a calibration of the vertical and lateral reaction forces is performed for different over travel distances and needle geometries. Dynamical results of simulation are in good agreement with experimental measurements. The analysis shows that inertial effects during probing process remain limited. In addition to that, the measured force features are well reproduced by modeling, particularly the fine effects observed during the unloading stage. Finally, the effect of aluminium mechanical behavior is discussed by introducing permanent deformation ability of the pad.

This paper discusses the optimization of series resistance of nonplanar metal-insulator-metal capacitor, i.e., an original 3-D capacitor with a capacitance density of 35 nF/mm 2 , used in very large scale integration. A fully analytical and physically based model of its series resistance versus material and geometrical parameters has been developed, in excellent agreement with both 3-D numerical simulations and experiments. Based on the modeling results, possible design strategies of series-resistance reduction are suggested; showing a reduction of the series resistance by approximately a factor of four, without any degradation of the capacitance density

This paper summarizes the electrical characterization of MIM capacitor realized in three-dimensional. High density of 35nF/mm 2 is obtained with low leakage current. Its integration in BiCMOS technology is demonstrated and three circuits are characterized

RF and analog designs require high performances MIM capacitors. In order to continue downscaling of MIM devices, we have developed and integrated a 3D damascene MIM capacitor in the copper back-end of a 0.13 mum BICMOS technology. Si3N4 has been used as dielectric to reach excellent performances for a 5 fF/mum2 capacitance density in term of leakage current, voltage linearity, dielectric relaxation, and reliability. This 3D architecture is a very promising candidate to carry on capacitance density increase.

Integrated circuits for analog and telecom applications require metal insulator metal (MIM) capacitors with not only a high capacitance value (typically 5nF/mm2), but also a low series resistance Rs. The optimization of this latter parameter is investigated in this paper, by means of a simple analytical model, taking into account both the impact of material parameters and device architectures, suggesting possible strategies for Rs minimization. Such a model is also suitable for MIM circuit simulation, and can be also extended to other devices, such as to the gate series resistance modeling of RF MOSFET. Results are in good agreement with numerical simulations and HF measurements, performed on state of the art planar MIM devices. Moreover, discussion on via placement to access the top electrode has been held, in order to optimize the series resistance of the capacitor.

When deposited by chemical vapor deposition (CVD), TiN layers must be post-treated with N"2/H"2 plasma. Metal-insulator-metal (MIM) capacitors using CVD-TiN as electrodes and Al"2O"3 as insulator are studied from both electrical and physico-chemical points of view. We verify that N"2/H"2 plasma is efficient concerning the TiN layers, while ensuring a low and uniform resistivity. However, the MIM capacitor figures of merit are impacted by the N"2/H"2 plasma, especially by the top electrode post-treatment. In particular, capacitance at 0V has been found to increase with TiN post-treatment, as well as the quadratic linearity coefficient. As for leakage currents, the top electrode densification induces non-standard mechanism and trapping phenomenon. Finally, the dielectric relaxation is also degraded when top electrode is post-treated. Electron energy loss spectroscopy (EELS) shows that the top electrode post-treatment is associated to Nitrogen diffusion, from the TiN top electrode into the alumina. Thus, chemical interactions between top electrode and alumina layer, induced by the top electrode post-treatment, may be at the origin of such behaviours.

This paper describes realization and characterization of SrTiO3 (STO) high k MIM capacitors above BiCMOS integrated circuit (IC). These capacitances are connected to IC and are used as coupling capacitors