This paper discusses an innovative architecture of charge storage NVM cell, which outpaces state-of-the-art in term of bit-cell area. This new concept of memory cell is used today in production for microcontrollers. After cell architecture and activation description, we will present process flow integration challenges, process optimizations and single cell characterizations.

This paper presents a new solution to reduce the mechanical stress impact of Shallow Trench Isolation (STI) by adding polysilicon in STI and thus, improve MOSFET performances. Indeed, when a polysilicon wall is used, the drive current of NMOS transistors used in analog and digital applications is 5% higher due to the reduction in the STI-induced, compressive stress in the channel. The polysilicon wall could be added automatically in digital standard cells during cad to mask operation without increasing the size of the cells. Finally, the speed frequency of CMOS inverter ring oscillators designed with low-voltage MOSFETs used in digital standard cells is increased by 6% when a polysilicon wall is added around NMOS transistors. Moreover, the static current of ring oscillators remains unchanged.

In this paper, carrier effective mobility is accurately extracted from weak to strong inversion and from ohmic to saturation regimes by pairing the split C-V technique with charge-sheet model. In weak inversion, both electron and hole effective mobility are found to be constant and V-DS independent. Moreover, effective mobility extracted by this new method is modeled in all regimes using already published models extended up to the saturation regime. (C) 2015 Elsevier Ltd. All rights reserved.

This paper presents several layout optimizations in order to decrease both, the internal power and the area of digital standard cells. A new D flip-flop (Dff) is designed using advanced design rules and lower active widths. Post-layout simulations are performed and the internal power of a new Dff is reduced by 20% while clock-to-Q delay remains unchanged. Indeed, a new optimized process based on e-NVM (embedded Non-Volatile Memory) CMOS 80 nm technology is developed. The saturation current (IDSAT) is improved by 15% and 50% for NMOS and PMOS transistors, respectively. Moreover, the area of the new Dff is reduced by 20% by using lower active widths and new optimized design rules.

In this paper, we show that performances of Ge2Sb2Te5-based phase-change memory (PCM) cells can be improved by the insertion of a thin HfO2 interfacial layer between the phase-change material and the tungsten plug. Significant reduction of the RESET and SET currents and of the energy required to switch the PCM cells are demonstrated. In addition, compared with pure GST reference cells, the presence of the HfO2 layer leads to an enhanced endurance (>108 cycles) and an improved data-retention (ten years at 172°C). Using cross-sectional TEM-Energy Dispersive X-Ray (EDX) analyses and technology computer-aided design simulations, the decreases of the programming currents and energy are explained through the reduction of the PCM cell active area, due to the creation of conductive paths in the HfO2 layer during the initial forming procedure. Electrical measurements and modeling of the forming procedure indicate that the size of the conductive paths is controlled by the maximum current flowing through the PCM cells during the current overshoot of the forming procedure.

In this paper, we show that performances of Ge2Sb2Te5-based phase-change memory (PCM) cells can be improved by the insertion of a thin HfO2 interfacial layer between the phase-change material and the tungsten plug. Significant reduction of the RESET and SET currents and of the energy required to switch the PCM cells are demonstrated. In addition, compared with pure GST reference cells, the presence of the HfO2 layer leads to an enhanced endurance (>10(8) cycles) and an improved data-retention (ten years at 172 degrees C). Using cross-sectional TEM-Energy Dispersive X-Ray (EDX) analyses and technology computer-aided design simulations, the decreases of the programming currents and energy are explained through the reduction of the PCM cell active area, due to the creation of conductive paths in the HfO2 layer during the initial forming procedure. Electrical measurements and modeling of the forming procedure indicate that the size of the conductive paths is controlled by the maximum current flowing through the PCM cells during the current overshoot of the forming procedure.

In this paper, we investigate the performances of carbon-doped Ge2Sb2Te5 films (named hereafter GST) which have been integrated together with a thin titanium capping layer into Phase-Change Memory devices. We show that the carbon content into GST and the titanium cap layer thickness can be optimized to obtain an Amorphous As-Deposited (A-AD) phase which is stable under both the typical Back End-Of-Line (BEOL) thermal budget (2 min at 400°C) and standard Pb-free soldering reflow process conditions (temperature peak at 260°C). Therefore, the material obtained at fab-out keeps its disordered phase and can be used to precode one state of information stable against the standard soldering reflow (peak at 260°C). We propose to use this high resistance state together with an electrically induced low resistance state to pre-code the memory prior to PCB manufacturing.

In this paper, carbon-doped Ge2Sb2Te5, integrating from 5% to 15% of carbon content, is studied as an alternative phase-change material. Accurate electrical characterizations were performed both on large and shrinked PCM devices. Compared to pure Ge2Sb2Te5 based reference devices, a wide decrease of about 50% of the RESET current, which translates into a RESET power reduction of about 25%, is observed when 5% of carbon is added to Ge2Sb2Te5. Moreover, an improved endurance up to 108 cycles is obtained while maintaining a programming window higher than 2 orders of magnitude. An increase of about 30% of the activation energy for the crystallization process is also observed. Therefore, this paper suggests that Ge2Sb2Te5 doped with 5% of carbon is a promising phase-change material for future PCM technology.

In this work, we will focus on the use of Phase Change Memory (PCM) to emulate synaptic behavior in emerging neuromorphic system-architectures. In particular, we will originally show that the performance and energy-efficiency of large scale neuromorphic systems can be improved by engineering individual PCM devices used as synapses. This is obtained by adding a thin HfO2 interface layer to standard GST PCM devices, allowing for the lowering of the Set/Reset currents and the increase of the number of intermediate resistance states (or synaptic weights) in the synaptic potentiation characteristics. The experimentally obtained potentiation characteristics of such PCM devices are used to simulate a 2-layer ultra-dense spiking neural network (SNN) and to perform a complex visual pattern extraction from a test case based on real world data (i.e. cars passing on a 6-lane freeway). The total power dissipated in the learning mode, for the pattern extraction experiment is estimated to be as low as 60μW. Average detection rate of cars is found to be greater than 90%.

In this paper, a detailed investigation of the electrical performances of Phase-Change Memory test devices integrating carbon-doped Ge2Sb2Te5 (named GST-C) is reported. PCM devices with 5% of carbon atomic content yields more than 50% of current reduction compared to reference GST devices, with a programming window widely superior to two orders of magnitude and a cycling endurance up to 108 cycles. The reset current reduction is finally validated on shrinked "μ-Wall" test devices, proving that carbon- doped GST is a high promising material for future PCM technology.

In this paper, we present a thorough physical-chemical analysis of an engineered PCM stack, where the integration of C-doping and the use of a Ti top layer allow obtaining an Amorphous As-Deposited (A-AD) phase stable against Back End-Of-Line (BEOL) thermal budget. This PCM stack is then integrated in devices, which are extensively tested in order to validate a novel pre-coding technique compliant to the Pb-free soldering reflow issue. Finally, an original design to optimize the distribution dispersion is presented.

The physical mechanisms that regulate carrier transport in polycrystalline chalcogenides, such as Ge2Sb2Te5 (GST), are still debated. Recently, self-induced Joule-heating (SJH) effect has been claimed to be the key factor in explaining the nonlinearity of the I-V characteristics of polycrystalline GST-based phase-change memory (PCM). In this paper, we carefully investigate the SJH occurring in the GST material by analyzing the I-V characteristics of PCM cells at low voltages, i.e., in the memory-cell readout region. To accomplish the study, we use ad hoc fabricated PCM devices allowing an easier evaluation of SJH occurring in the chalcogenide layer. A novel procedure to test the SJH effect is also proposed. A comparison between numerical simulations and compact modeling is discussed as well. Our paper shows that the SJH effect is not sufficient to reproduce the experimental I-V nonlinearity, claiming for new experiments and theoretical investigations. Therefore, this paper can be considered a step forward toward the comprehension of the transport properties of polycrystalline GST, which is a key aspect for robust modeling of PCM devices.

In this work, we will focus on the use of phase change memory (PCM) to emulate synaptic behavior in emerging neuromorphic system-architectures. In particular, we will show that the performance and energy-efficiency of large scale neuromorphic systems can be improved by engineering individual PCM devices used as synapses. This is obtained by adding a thin HfO2 interface layer to standard GST PCM devices, allowing for the lowering of the Set/Reset currents and the increase of the number of intermediate resistance states (or synaptic weights) in the synaptic potentiation characteristics. The experimentally obtained potentiation characteristics of such PCM devices are used to simulate a 2-layer ultra-dense spiking neural network (SNN) and to perform a complex visual pattern extraction from a test case based on real world data (i.e. cars passing on a 6-lane freeway). The total power dissipated in the learning mode, for the pattern extraction experiment is estimated to be as low as 60 mu W. Average detection rate of cars is found to be greater than 90%. (C) 2012 Elsevier Ltd. All rights reserved.