This paper presents a new solution to reduce the mechanical stress impact of Shallow Trench Isolation (STI) by adding polysilicon in STI and thus, improve MOSFET performances. Indeed, when a polysilicon wall is used, the drive current of NMOS transistors used in analog and digital applications is 5% higher due to the reduction in the STI-induced, compressive stress in the channel. The polysilicon wall could be added automatically in digital standard cells during cad to mask operation without increasing the size of the cells. Finally, the speed frequency of CMOS inverter ring oscillators designed with low-voltage MOSFETs used in digital standard cells is increased by 6% when a polysilicon wall is added around NMOS transistors. Moreover, the static current of ring oscillators remains unchanged.

In this paper, carrier effective mobility is accurately extracted from weak to strong inversion and from ohmic to saturation regimes by pairing the split C-V technique with charge-sheet model. In weak inversion, both electron and hole effective mobility are found to be constant and V-DS independent. Moreover, effective mobility extracted by this new method is modeled in all regimes using already published models extended up to the saturation regime. (C) 2015 Elsevier Ltd. All rights reserved.

This paper presents an original solution to decrease significantly the power consumption of CMOS digital circuits. The supply voltage VDD and the MOSFET width are reduced and allow lowering the dynamic current of circuits by 25%. A CAD-to-mask script was developed in order to automatically reduce all physical widths of low-voltage transistors used in standard cells. With this operation, no additional redesign of standard cells was necessary. Moreover, a new optimized process based on e-NVM (embedded Non-Volatile Memory) CMOS 80 nm technology is developed. ION current is improved by 15% and 50% for NMOS and PMOS transistors, respectively. This, let us decrease dynamic current without impacting circuit performance. Finally, the static current of the circuit is reduced by 60% through design and process optimization.

This paper presents several layout optimizations in order to decrease both, the internal power and the area of digital standard cells. A new D flip-flop (Dff) is designed using advanced design rules and lower active widths. Post-layout simulations are performed and the internal power of a new Dff is reduced by 20% while clock-to-Q delay remains unchanged. Indeed, a new optimized process based on e-NVM (embedded Non-Volatile Memory) CMOS 80 nm technology is developed. The saturation current (IDSAT) is improved by 15% and 50% for NMOS and PMOS transistors, respectively. Moreover, the area of the new Dff is reduced by 20% by using lower active widths and new optimized design rules.

This paper presents a way to implement a test structure able to measure accurately a large number of threshold voltage values for Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) matching characterization. A multiplexed system able to select a single transistor among others in a small array is used. This architecture guarantees a similar environment for all transistors in the array, while requiring a small number of pads for measurement. Moreover, the influence of the multiplexer switches can be evaluated: their unwanted contribution to the measurement can therefore be compensated. An experimental study to evaluate the influence of this multiplexer on measurement and the efficiency of the compensation is conducted. Silicon results are presented in order to validate the concept.

In this paper, gate stress at high electrical field has been studied on High Voltage MOSFETs used for Non-Volatile Memory applications. Charge pumping measurements and characteristic Capacitance-Voltage have been applied to demonstrate that degradation mechanism of n-and p-channel transistors is firstly due to charge fixed trapping by Anode Hole Injection, and then dependent on where electrons are injected, i.e. from gate or from substrate. Furthermore, low activation energy has been found for positive stress on n-and p-MOSFETs.

This paper describes different solutions to decrease dynamic consumption of circuits processed on an embedded non-volatile memories CMOS 80 nm technology. Up to 25 % in dynamic power reduction is demonstrated without degrading performances and static leakages of devices and above all, with full DMR compliancy. Ring oscillator designs are used to estimate the dynamic power gain, comparing new development process (B) to reference process (A) currently in use in manufacturing.

In this paper, gate stress has been studied on High Voltage p- and n-MOSFETs used for Non-Volatile Memory applications. For the first time, a higher degradation on n-channel transistor compared to p-channel transistor has been observed. Time dependence, recovery effect, voltage acceleration factor and activation energy have been evaluated.

Hump effect has been widely studied but it is still present on technology presenting "thick oxide". In this paper, two MOSFET layout modifications have been studied in order to suppress hump effect. We have used a statistics method of parametric measurement to reveal the hump effect removal on short transistors of both devices. In order to explain these results, TCAD simulations in three dimensions have been run and have demonstrated that the hump effect can be removed due to modification of the bending of current lines along the channel. Moreover, we demonstrated that the reliability performances are not impacted by these designs. (C) 2013 Elsevier B.V. All rights reserved.

On CMOS technology, some process steps can create a parasitic phenomenon named “hump effect.” This parasitic effect can have a strong impact on gate voltage matching of differential pairs and, as a consequence, on analog circuit performances. In this context, several solutions to limit or remove this hump effect are proposed and described. Silicon data obtained at package and wafer levels for different temperatures are analyzed.

In this paper, the electrical instabilities of Inter Metal Dielectric (IMD) SiOCH are investigated. These instabilities concern leakage current between metal lines and dielectric breakdown. At room temperature IMD leakage current tends to increase with waiting time. At high temperature and without electrical stress, a defect recovering phenomenon occurs and leakage current decreases. Depending on the applied electrical field, different conduction mechanisms are activated. At low field, Ionic conduction predominates, whereas at high electric field, Poole-Frenkel conduction is predominant. Comparing data and simulation results, ion activation energy is estimated. Then, presence of alkaline ions in SiOCH is suggested as the cause of electrical instabilities. Finally, Time Dependent Dielectric Breakdown (TDDB) is modeled as a function of initial leakage current and stress voltage bias.

For CMOS technology, the increase of interconnects metal density is responsible for heterogeneous mechanical stress fields in active regions of silicon. Coupled mechanical–electrical measurements are performed to evaluate the impact of stress at circuit and device levels. This mismatch originated by interconnects metal lines stress is measured through the use of piezoresistive test structures. Local mechanical stress can thus be monitored in a simple process control compatible approach.

To improve analogue circuit reliability, the evolution of VT and VT matching under hot carrier injection (HCI) stress has been investigated on standard and octagonal MOSFETs. An important degradation can be observed on standard devices due to the presence of parasitic corner transistors. The specific structure of octagonal MOSFETs removes parasitic transistors and reduces VT degradation. Moreover, the residual VT degradation of octagonal MOSFETs, which is asymmetric, is further reduced by reversing source and drain connections.

Low power analog applications are often designed under threshold and can be degraded by hump effect. This effect is explained through device dimensions and body bias studies. A MOSFET matching improvement in sub-threshold area is demonstrated with active “multi-fingers” test structure.

This paper demonstrates how poly-Silicon gate pre-doping implantation impacts MOS matching performances. Measurements are performed on test structures (MOS pairs / capacitors) and analog circuits, using five different processes with pre-doping implantation energy variation (from 35 to 10 KeV) and tilt variation (7° and 25°). TCAD simulations validate a channel counter-doping due to high pre-doping implantation energy causing mismatch degradation.

For CMOS technology, the increase of interconnects metal density is responsible for heterogeneous mechanical stress fields in active region of silicon. This mismatch originated by interconnects metal lines stress is measured through the use of piezo-resistive test structures. Local mechanical stress can thus be monitored in a simple process control compatible approach.

Low power analog circuits needs large and short MOSFETs biased in the sub-threshold area with good performances in terms of matching. In order to reach these specifications, octagonal transistors are proposed. Due to their design, these transistors avoid hump effect. As a consequence, gate-source voltage matching under-threshold is always at its best level. Moreover, the paper shows the device robustness to hot carrier stress is improved on octagonal NMOS; V T matching degradation due to hot carrier stress is also improved with an octagonal design.

In this paper we investigate the energy consumption of Discrete-Trap Silicon Nanocrystal (Si-nc) Nonvolatile Memory Cell during Channel Hot Electron programming operation. We compare this cell with a Floating Gate Flash in order to evaluate the current absorption and the energy consumption under different conditions. Using a commercial TCAD simulator, a good agreement between data and simulations is obtained and the involved mechanisms are analysed. Then we propose a solution to optimize the programming window and energy consumption trade-off for Si-nc Flash Cells.

Analog circuit designs are often biased to work in sub-threshold mode for low power constraints and for better gate-source voltage matching performances. Depending on process, hump effect may change MOS characteristics for negative Bulk-Source Voltage (VBS) and have a slight impact for VBS=0V. Actually, even without body effect, hump mainly degrades MOS matching performances in the sub-threshold area with significant temperature dependence. Thus, in order to accurately simulate bandgap performances, modeling of hump effect has to be considered.