This work presents the effects of silicon film thickness on analog performance on a FDSOI transistor. The increase of silicon film thickness leads to higher carrier mobility with possible impact on electrostatic control. The optimum condition has been identified for T Si =16nm, with maximum mobility gain and -15% RTN noise reduction. Additionally, by connecting the front-gate and back-gate together, we show the possibility of further improving the intrinsic gain up to +36% and reducing the RTN noise by -45%.

This paper describes a 22nm FDSOI technology optimized for RF/mmWave applications. The offering consists of high speed mmWave FET transistors, and a thick dual copper back-end. The offering is integrated with a low power digital technology (0.4V) and is extremely simple with less than 40 masks for an 8M process. The best performance for nFET/pFET f T is 347/275 GHz and for f MAX is 371/299 GHz. The RF cell layouts enable higher performance and improved wiring flexibility for the higher currents demanded in mmWave applications. The optimized pFET layout utilizes stress to increase performance while minimizing the parasitic capacitance. A strong pFET distinguishes this technology from many others enabling more efficient “complementary” RF/mmWave design. This combination of high performance mmWave FET transistors, low voltage logic, and low complexity mask build makes it ideal for a large suite of RF/mmWave application including IOT, 5G, and Radar.

The aim of this study is to illustrate the efficiency of TCAD for simulating RF devices in advanced technology nodes and identify optimization paths. A strategy involving 3D simulation and a multilayered description of the resistive gate is proposed, followed by a calibration step of the TCAD setup against measurements. Then, various effects impacting the values of the Ft/Fmax RF figures of merit are assessed. At last, thanks to combination of TCAD with Design of Experiments, the sensitivity analysis of the most influent process parameters as well as their interactions is performed.

22FDX™ is the industry's first FDSOI technology architected to meet the requirements of emerging mobile, Internet-of-Things (IoT), and RF applications. This platform achieves the power and performance efficiency of a 16/14nm FinFET technology in a cost effective, planar device architecture that can be implemented with ~30% fewer masks. Performance comes from a second generation FDSOI transistor, which produces nFET (pFET) drive currents of 910μ/μm (856μ/μm) at 0.8 V and 100nA/μm Ioff. For ultra-low power applications, it offers low-voltage operation down to 0.4V V min for 8T logic libraries, as well as 0.62V and 0.52V V min for high-density and high-current bitcells, ultra-low leakage devices approaching 1pA/μm I off , and body-biasing to actively trade-off power and performance. Superior RF/Analog characteristics to FinFET are achieved including high f T /f MAx of 375GHz/290GHz and 260GHz/250GHz for nFET and pFET, respectively. The high f MAx extends the capabilities to 5G and milli-meter wave (>24GHz) RF applications.

We have physically and electrically characterized pMOSFETs of compressively strained SiGe channel built on Ultra-Thin-Body and Buried-Oxide Fully-Depleted-Silicon-On-Insulator (UTBB FDSOI). Such a channel greatly contributes to the FDSOI CMOS high-performance at the 14nm node. At the same time, it induces strong layout effects, which are reported and explained in this paper. They can be reproduced by an accurate physics-based electrical model, which enables us to predict the device and design performance for various technological configurations: germanium concentration in the channel, isolation and channel process integration. In order to mitigate the impacts of the SiGe channel relaxation, we have studied two kinds of solutions. First, technological solutions are possible, leading experimentally to a -15 percent delay reduction for a ring-oscillator of 1-gate finger inverters at 0.8V supply voltage. Secondly, we demonstrate the benefits induced by smart design layouts, enabled by process integration goodies and some layout constructs. Namely, a continuous-RX design, which consists in a long active line configuration, optimizes the stress configuration, maintaining a high level of longitudinal compressive stress, while relaxing the transverse one. A 28 percent ring oscillator delay improvement is experimentally demonstrated at a given leakage for 1-finger inverter at 0.8V supply voltage. This demonstrates the interest of process/design co-optimization of strain-induced layout effects. Finally, we discuss the technological knobs and especially the strain boosters that can furthers the scaling of FDSOI below the 14nm node: SiGe channel and source/drain of high-Ge content, influence of the surface orientation and channel direction, as well as the gate last integration.

High-speed circuits, as well as highly-efficient power management and process compensation techniques were already demonstrated on planar FDSOI [1-3]. This is enabled by CMOS devices of high-performance, low-variability, high bodyfactor, as evidenced at the 28nm and 14nm nodes [4-5]. In this abstract, we will start describing the 14nm FDSOI technology and devices we have developed, and then focus on some technology knobs that could be useful in the future in order to scale this architecture down to the 10nm node, namely the body and buried oxide scaling, the strain-SOI substrates (sSOI) and the gate last introduction.

Radar Cross Section (RCS) measurements of a target should be useful for each orientation angle of the target. Usually, measurements in an anechoic chamber on a classical styrofoam mast provide RCS data as a function of only one roll and one elevation cuts. In order to characterize full 3D near field monostatic RCS of small targets, an indoor experimental layout has been developed in CEA/CESTA. This measurement facility is composed of a motorized rotating arch holding the measurement antenna, operated over the range [2GHz, 12 GHz] for both HH and VV polarizations. The radar range equal to 4 meters. To quantify the capability of this layout to characterize the full 3D near field monostatic RCS of a target, a model has been developed, including the near-field illumination of the measurement antenna. This paper describes the implemented software and how the near field illumination is simulated over the operating frequency range. Comparisons between simulations and measurements of a canonical target are finally presented.

This paper presents mechanical simulations results of an innovative strain transfer structure consisting in a buried compressive SiGe layer embedded under an ultra-thin buried oxide (BOX). We studied the influence of different dimensions including the active area and determined optimal parameters of the SiGe layer maximizing the strain. We demonstrate a transfer of a tensile stress up to 1.3GPa in the silicon. Thanks to 3D simulations and the study of stress profiles in the SOI, the electron mobility enhancement is estimated to be about 80% for logic transistors at the 10nm node. The strain induced in the channel by the edge relaxation of an embedded buried SiGe layer is compared to strained Silicon-On-Insulator (sSOI) wafers and strained nitride layer for Fully Depleted Silicon-On-Insulator (FDSOI).

This paper presents mechanical simulations results of an innovative strain transfer structure. The strain induced by the edge relaxation of a buried SiGe layer is compared to strained SOI (sSOI) wafers for Fully Depleted Silicon-On-Insulator. We studied the influence of different dimensions including the active area and demonstrate a transfer of a tensile stress up to 1.3GPa in the Silicon, corresponding about 80% electron mobility enhancement for logic transistors at the 10nm node.

We present for the first time Gate-Last (GL) planar Fully Depleted (FD) SOI MOSFETs featuring both ultra thin silicon body (3-5 nm) and BOX (25 nm). Transistors with metal-last on high-k first (TiN/HfSiON) have been successfully fabricated down to 15nm gate length. We have thoroughly characterized the gate stack (reliability, work-function tuning on Equivalent Oxide Thickness EOT=0.85nm) and transport (hole mobility, Raccess) for different surface and channel orientations. We report excellent ION, p=1020μA/μm at IOFF, p=100nA/μm at VDD=0.9V supply voltage for <;110> pMOS channel on (001) surface with in-situ boron doped SiGe Raised Source and Drain (RSD) and compressive CESL. This is explained by the high efficiency of the strain transfer into the ultra-thin channel, as evidenced by physical strain measurements (dark field holography).

We integrated planar fully depleted (FD) SOI MOSFETs with a gate-last on high-k first (GL-HKF) down to gate lengths of Lg = 15 nm and active widths of W = 80 nm. Such an integration scheme enables reaching for pMOSFETs a threshold voltage of V-Tp = 0.2 V and one decade gate current (J(G))gain, as well as similar hole mobility and ON-currents, compared to pMOSFETs integrated with a gate first. This approach is also benchmarked with high-k last (GL-HKL) stacks in terms of leakage, equivalent oxide thickness (EOT), effective work-function (EWF) and flat band voltage (V-FB) shift under stress. (C) 2013 Elsevier B.V. All rights reserved.

We have evaluated various Cyclic Selective Epitaxial Growth/Etch (CSEGE) processes in order to grow "mushroom-free" Si and SiGe:B Raised Sources and Drains (RSDs) on each side of ultra-short gate length Extra-Thin Silicon-On-Insulator (ET-SOI) transistors. The 750 degrees C, 20 Torr Si CSEGE process we have developed (5 chlorinated growth steps with four HCl etch steps in-between) yielded excellent crystalline quality, typically 18 nm thick Si RSDs. Growth was conformal along the Si3N4 sidewall spacers, without any poly-Si mushrooms on top of unprotected gates. We have then evaluated on blanket 300 mm Si(001) wafers the feasibility of a 650 degrees C, 20 Torr SiGe:B CSEGE process (5 chlorinated growth steps with four HCl etch steps in-between, as for Si). As expected, the deposited thickness decreased as the total HCl etch time increased. This came hands in hands with unforeseen (i) decrease of the mean Ge concentration (from 30% down to 26%) and (ii) increase of the substitutional B concentration (from 2 x 10(20) cm(-3) up to 3 x 10(20) cm(-3)). They were due to fluctuations of the Ge concentration and of the atomic B concentration [B] in such layers (drop of the Ge% and increase of [B] at etch step locations). Such blanket layers were a bit rougher than layers grown using a single epitaxy step, but nevertheless of excellent crystalline quality. Transposition of our CSEGE process on patterned ET-SOI wafers did not yield the expected results. HCl etch steps indeed helped in partly or totally removing the poly-SiGe:B mushrooms on top of the gates. This was however at the expense of the crystalline quality and 2D nature of the similar to 45 nm thick Si0.7-Ge0.3:B recessed sources and drains selectively grown on each side of the imperfectly protected poly-Si gates. The only solution we have so far identified that yields a lesser amount of mushrooms while preserving the quality of the S/D is to increase the HCl flow during growth steps. (C) 2013 Elsevier Ltd. All rights reserved.

Nanoelectronics will have to face major challenges in the next decades in order to proceed with increasing progress to the sub 10 nm nodes level and face the challenge to approach zero variability. The main requirements will be to reduce leakage currents and reduce access resistances at the same time in order to fully exploit 3D integration at the device, elementary function, chip and system. New progress laws combined to the scaling down of CMOS based technology will emerge to enable new paths to Functional Diversification. New materials and disruptive architectures, mixing logic and memories, Heterogeneous Integration, introducing 3D schemes at the Front End and Back End levels, will come into play to make it possible.

We fabricated highly stressed FDSOI pMOSFETs down to 15nm gate length. The impact of different stressors (CESL, raised sources and drains, STI) is studied for different device geometries and channel orientations (<;100>; or <;110>;). We evidence that pMOSFETs along <;110>; are more sensitive to stress: STI degrades narrow devices compared to wide ones whereas compressive CESL (-3GPa) and SiGe S/D improve performances (+133% mobility, +16% ION on 10μm wide devices). This makes the <;110>; orientation the most favorable channel orientation for strained pMOSFETs on planar FDSOI.

We fabricated highly stressed FDSOI nMOSFETs down to 18nm gate length. The impact of different stressors (CESL, STI) is studied for different device geometries and substrates orientation (<;100>; or <;110>;). We evidence that STI degrades wide devices of intermediate gate length (0.2μm<;L G <;1μm) along <;100>; compared to <;110>; (-20% mobility) whereas short nMOSFETs are improved along <;100>; with a (1.6 GPa) tensile CESL (+15% mobility, +6% I ON ). The CESL-induced mobility enhancement can be reproduced rather well for the two channel orientations by the piezo-resistive model and an analytical model of the stress profile.

We fabricated highly stressed Fully Depleted Silicon-On-Insulator (FDSOI) n and pMOSFETs reaching I ON,n /I ON,p =1148/1014μA/μm drive current at I OFF,n /I OFF,p =55/16nA/μm leakage current (V DD =1V) with excellent V T -matching (A VT <; 1.5mV.μm). These short channel performances are well correlated and quantitatively explained by the effectiveness of strained SOI (sSOI), Contact-Etch-Stop-Layers (CESL) and SiGe raised sources and drains. sSOI improves I ON,n up to 22% and degrades SiGe sources and drains efficiency for pMOSFETs. However, 0° (<;110>;) orientation remains the best configuration for high-stress pMOSFETs and provides the best trade-off for CMOS.

The PW scattering-matrix theory, originally introduced by Kerns and Dinallo, enables to evaluate the far-field scattering matrix of a target from a near-field illumination and near-field measurements of the scattered field. It compensates the near-field effects as well as the own characteristics of the near-field setup. The mathematical processing, which is used to evaluate the far-field scattering matrix, has been developed step by step. This mathematical extraction requires planar near-field measurements of the field scattered by the target. It also requires the near-field setup to be calibrated. Two different calibration methods have been developed. The first one is based on a two or three-antenna technique and requires a limited number of measurements. The second one uses bistatic RCS measurements. The PW scattering-matrix theory will now be experimented.

In this Note, we return to the theory of characteristic modes which was introduced 30 years ago for electromagnetic scattering problems. A simple mathematical framework is proposed and complete definitions are given. The potential interest of this theory in terms of Radar Cross Section (RCS) analysis is then discussed, especially in the low frequency case. Finally, a 3-D example is presented to illustrate the efficiency of this decomposition. (C) 2004 Academie des sciences. Publie par Elsevier SAS. Tons droits reserves.