Nano-electro-mechanical circuits exhibit attractive resilience to radiation and high temperature, but suffer from wear-out. Previous studies have already proven that self-timed circuit design is a promising choice to extend their lifetime. This paper presents an exploration of different protocols and design styles on different sets of available NEM switch types as a foundation for identifying the most suitable choice.
Marino (IEEE ToC,1977) developed an equivalent circuit to describe the output behavior of a Schmitt Trigger. This beautifully simple model has proven specifically useful for investigating the metastable regions of this device. However, with its few and idealized analog components, it fails to reflect certain (metastable) behaviors of real-world Schmitt Trigger implementations. In this paper we augment Marino’s approach by amplifiers in the feedback- and in the input path to extend its modeling capabilities towards such behaviors. Our simulation results confirm the desired expressive power of our new model that not only allows to cover a wider range of observed Schmitt Trigger output characteristics, but also facilitates modeling additional related other circuits, e.g., the D-latch. The characterization effort is still low, relying on at most seven values that can be extracted from the (meta)stable states.
Several recent projects have proposed approaches to traffic engineering that schedule workloads to maximize the idle time of network equipment in order to reduce overall power consumption. However, today’s switches and network interface cards (NICs) consume significant power even while idle. This power inefficiency both increases operational costs and has a tremendous environmental impact. The key obstacle in realizing an energy proportional switch is physical link performance, i.e., creating a high-speed SERDES (serialization/deserialization) link.Asynchronous circuit designs, which do not rely on a global clock, make any digital computation energy proportional by their nature. However, asynchronous SERDES design is a relatively unexplored topic. In this paper, we improve on a previous SERDES design to incorporate continuous-time equalization hardware and circuit-level optimizations for the digital processing that takes the data rate to 20 Gbps in a 65nm technology. Through circuit simulation, we demonstrate that the SERDES link is energy proportional. Overall, this is an important step towards designing energy-proportional network switches and NICs.
Flexible integrated circuits (FlexICs) fabricated on metal-oxide thin-film transistor processes suffer from substantial process variability, making asynchronous design an attractive approach: self-timed circuits adapt to actual gate delays rather than relying on worst-case timing margins. Validating such circuits at wafer scale, however, requires test infrastructure capable of exercising delay-insensitive handshake protocols, detecting per-channel faults, and capturing timestamped signal traces across thousands of die sites. This paper presents an FPGA-based testbench for automated wafer-level testing of asynchronous FlexICs synthesised with the ALHO self-timed template. The testbench implements the full four-phase dual-rail handshake protocol, provides per-channel timeout-based fault detection, in-hardware golden-result verification, and cycle-accurate event capture. A backpressure mechanism freezes the handshake controller when the event buffer fills, preventing data loss without requiring oversized FIFOs. The same infrastructure supports a synchronous variant of the same classifier design, enabling direct comparison of yield and maximum operating frequency across design styles. The complete system integrates FPGA control with automated wafer stepping, source-measure unit power sequencing, and probe-card touchdown verification for unattended full-wafer characterisation runs.
Asynchronous circuits offer potential advantages in low power and performance. To design reliable asynchronous circuits, the Design-for-Testability (DfT) is essential, since it enhances fault detection, reduces test costs, and improves yield and reliability. However, there is no automatic test pattern generation (ATPG) method for the DfT architecture of bundled-data circuits, and manual test pattern generation is impractical for large-scale asynchronous circuits. To solve this problem, we propose a graph-based ATPG method for the asynchronous DfT architecture (A-ATPG) to detect stuck-at, at-speed, and bubble faults. We verify the proposed DfT architecture and A-ATPG method on asynchronous Fork-Join, Fibonacci, greatest common divisor circuits, an asynchronous RISC-V-based spiking neural network (SNN) processor, and an asynchronous Network-on-Chip (NoC) circuit, respectively. Experimental results show that the stuck-at fault coverage achieves over 99%, bubble fault and at-speed fault testing cover all paths across multiple test cycles. The RISC-V-based SNN processor and the NoC circuit show a 0.6% and 12.7% area overhead, and 5.3% and 9.2% power overhead with the DfT architecture, respectively.
Synthesis of asynchronous circuits from CHP programs has seen significant improvements in recent times. We present several improvements and extensions to the state-of-the-art synthesis technique in order to further improve the performance of generated circuits and also provide designers with more power and flexibility. The proposed modifications are benchmarked against the baseline with pre-layout SPICE simulations of generated netlists. Comparison in a 65nm node show average improvements of 9% in area, 16% in delay and 23% in energy consumption.
Many of the inherent properties of Bundled-Data circuits can be leveraged for testing purposes, but are yet under-exploited in state-of-the-art designs. An approach in this direction is to halt the system during execution, which makes the system state observable and enables the implementation of controllability. Doing so without violating protocol correctness or causing metastability is challenging due to the absence of a global clock and the distributed nature of data propagation. This paper introduces the Jumper, a lightweight element that enables control and protocol-compliant halting of Bundled-Data pipelines. The element operates directly on asynchronous channels, where it stops transitions in a well-defined state while preserving data and protocol integrity. The Jumper has been studied in Weak Condition Half Buffer and Mousetrap pipelines, however it could easily be extended to other implementations. These pipelines have been validated through post-synthesis and analog simulations in a 28 nm Fully Depleted Silicon On Insulator technology. A two-stage RISC-V processor serves as a case-study for a system level design. The experimental results demonstrate that the Jumper introduces negligible area, power, and timing overhead, while enabling precise and repeatable debugging capabilities in asynchronous systems.
Wearable devices for physiological signal monitoring require low power consumption and adaptability to individual users. This adaptability necessitates on-chip learning to personalize models without relying on cloud resources. Spiking Neural Networks (SNNs) offer energy-efficient, event-driven processing, making them suitable for edge computing in such devices. However, implementing low-power and high-precision on-chip learning with SNNs on resource-constrained hardware remains challenging due to the high computational and memory demands. To address this challenge, this paper presents ANP-E, an asynchronous Spiking Recurrent Neural Network (SRNN) processor enabling on-chip learning for physiological signal monitoring. To minimize the power consumption of on-chip learning, we introduce two novel mechanisms for ANP-E: (1) an Update-Read mechanism that merges memory operations, reducing the number of input weight updates by 62.5%; and (2) a modified Eligibility Trace (ET) mechanism that further reduces the number of input and recurrent weight updates by 43.75% and 12.5%, respectively. ANP-E was fabricated using 22nm CMOS technology, occupying a core area of 1.14 mm2. Measurement results show classification accuracies of 99.48% for electroencephalogram (EEG), 99.25% for electrocardiogram (ECG), and 92.51% for electromyogram (EMG). The ANP-E achieves remarkable energy efficiency of 2.87 μW/MHz during inference and 3.315 μ W/MHz during on-chip learning, with measured power consumption of 0.663 mW during on-chip learning and 0.574 mW during inference at 0.8 V. These results verify the ANP-E’s capability to enable low-power, high-precision adaptive physiological signal monitoring in wearable devices.
Designing combinational logic for quasi delay-insensitive (QDI) circuits is challenging: data must be processed in encoded form (typically dual-rail), and circuits must be free of hazards and orphans. These constraints lead to significant hardware overhead compared to synchronous implementations.Binary comparator networks exhibit inherently monotonic, glitch-free switching behavior, which makes them well-suited as building blocks for QDI circuits. While previously limited to completion detection and symmetric Boolean functions, we extend their applicability by introducing generalized binary comparator networks (GBCNs), which can represent arbitrary logic functions.We present a complete synthesis flow that transforms conventional gate-level netlists into GBCN-based QDI circuits. Unlike DIMS, our approach uses only standard gates in the data path, with C gates confined to completion detection, resulting in lower latency. Evaluation on ISCAS-85 and EPFL benchmarks shows that our approach consistently outperforms Delay-insensitive Minterm Synthesis (DIMS) in area and latency, and is competitive to other reported approaches.
In the context of embedded systems, where energy consumption is of primary importance, minimizing circuit activity is a fundamental design imperative. The intrinsic event-driven nature of asynchronous Bundled-Data circuits makes them attractive candidates for such systems. However, the design of their synchronization logic remains challenging, as it involves a trade-off between control granularity and hardware design complexity. In contrast, synchronous circuits benefit from mature and automated clock gating insertion methodologies that effectively reduce switching activity. The present paper proposes the integration of clock gating into Bundled-Data asynchronous circuits, capitalizing on the strengths of both approaches. While Bundled-Data architectures enable global desynchronization of the system, clock gating provides fine-grained activity control without introducing prohibitive design overhead. To validate the proposed methodology, an asynchronous RISC-V processor has been implemented using STMicroelectronics 28nm FD-SOI technology. The post-synthesis results obtained for coarse-grain and fine-grain asynchronous control, as well as for the proposed mixed clock-gated approach, demonstrate the latter’s ability to achieve up to 74% power reduction and slight area savings while maintaining comparable throughput.
In circuit design, delay-insensitivity is regarded as a highly abstract ideal. Delay Insensitive (DI) circuits function correctly independent of specific operating conditions and avoid the need for many technology-specific details. However, their practical application is limited due to the necessity of manual design and the complexity inherent in creating a wide range of circuit features satisfying delay insensitivity.Recent theoretical advancements in the field have led to a re-evaluation of these assumptions. This work aims to address the remaining gaps between theory and practice by proposing an approach to move fully automated design processes as close to integrated DI circuits as possible. The ability to automatically synthesize abstract async Hardware Description Language (HDL) into circuit layout realizations fulfilling the requirements of abstract delay insensitivity for Place and Route (P&R) is enabled by these advancements. This work compares the competitiveness of DI-like designs in area and performance to the more common Quasi Delay Insensitive (QDI) and Bundled Data (BD) implementations, discusses the performance overhead in relation to bundled-data designs, and points out the feasibility and cost of delay insensitivity in automated synthesis.
Asynchronous Networks-on-Chip (NoCs) offer significant benefits in energy efficiency, area, and modularity, but their lack of compatibility with standard production test flows hinders industrial adoption. This paper demonstrates that a state-of-the-art 2-phase bundled-data asynchronous NoC (TaBuLA) can be transformed and made fully compliant with standard scan-based testing, enabling direct use of unmodified industrial ATPG tools and conventional ATE. Each asynchronous switch component is converted into a synchronous testable abstraction, addressing latch- and FF-related issues and meeting full controllability and observability requirements. As a result, a high-quality stuck-at fault coverage of 96.53% is achieved with a marginal 2% I/O pin count overhead. The unoptimized area, performance and power overheads (2.6x, 1.9x and at most 2x, respectively) achieve a more balanced trade-off between cost-coverage-industrial compliance than previous custom DFT infrastructures for asynchronous NoCs.
Asynchronous 4-phase Bundled-Data circuits are chosen for their low-power properties, ease of implementation and integration in commercial EDA contexts. However, their simplicity requires a Return to Zero phase that does not contribute to forward data propagation, which introduces a performance bottleneck. This work addresses this issue by proposing an asymmetric Current-starved Inverter delay element topology that shortens the Return to Zero phase while preserving functional behavior. To evaluate this approach, an asynchronous low-power RISC-V core is synthesized as a case study in STMicroelectronics 28 nm FD-SOI technology using a custom design flow that relies on standard EDA tools. The core was evaluated using both symmetric and asymmetric delay lines. Results show 58.6% higher performance in terms of Million Operations per Second compared to a symmetric standard cell delay element from the library. Finally, the effects on area and energy consumption have also been quantified using experimental results.
In this paper, we present the Asynchronous In-Place Optimisation (AIPO) algorithm, designed to enhance post-placement-and-routing (post-P&R) timing for asynchronous control and Bundled-Data circuits. AIPO operates in a closed-loop system with ASTA (Asynchronous Static Timing Analysis), focusing on achieving timing closure for the circuit. The algorithm performs gate resizing and buffer insertion by making tentative optimisation moves and evaluating their impact using ASTA. It leverages advanced timing models, such as CCS, and well-established wire RC representation formats, such as Pi-models. Additionally, AIPO works in tandem with a placement legaliser to resolve cell overlaps introduced by its optimisation actions. We present post-P&R results for the AIPO algorithm across 17 benchmark designs and three technology libraries: IHP 250nm, IHP 130nm, and GF 22nm. The results demonstrate that AIPO effectively improves circuit timing by mitigating the adverse effects of cell placement and wire RC interconnect delays. Timing improvements of 33% and 30% were observed for the IHP and GF libraries, respectively. The observed area overhead correlates with the achieved delay reductions, highlighting AIPO’s ability to navigate the Area-Delay Pareto trade-off effectively.
Event cameras asynchronously output a stream of words that encode the location, time, and sign of a luminance change that a pixel detects. When these events are sparse, one is read out of a 1024-by-1024-pixel with a 352ns latency, the time it takes to cycle from one row to another. But when more than one event occurs per cycle, this readout latency balloons to 180 mu s, the time it takes to cycle through half of the rows. Here we shorten this queue by reading out single events faster. Instead of selecting and addressing rows and columns, we select and address squares of exponentially increasing size. A 5-level-16-ary tree merges these squares' events hierarchically in a predetermined order. Asynchronous pipeline stages break up long datapaths to output a 16-bit word every 5ns, read an event out with a 51ns latency, and stream out events from all 1M pixels in 350 mu s (3.0Geps). By reading a single event out 7 times faster than row-column, hierarchical shortens the queue 500-fold and cuts latency 3,500-fold.
In this paper, we propose a novel approach for designing an asynchronous-based Bitwise Elimination Argmax (BEA) with early completion features catered for event-driven machine learning (ML) applications, and a novel software tool called GRAPHRACK for high-level analysis of distributed, yet parallel, asynchronous designs of graph-based models like Petri nets (PNs). Typically in ML architectures, the Argmax functions to find the largest vector within an input set can be a costly operation and size inefficient, especially for bespoke low-latency ML architectures. By introducing an asynchronous BEA, we address the above with an 'in the race' style protocol, where vectors are competed against one another and are procedurally eliminated from the most to least significant bits, with high-confidence classification vectors winning the fastest. This asynchronous BEA component is implemented using PNs and is tested against two benchmark scenarios: randomly distributed vectors and Tsetlin Machine (TM) class sum data. We also introduce GRAPHRACK's simulation platform that accelerates the analysis of PN models. Here, our results show average-case performance improvements of 1.52x over worst-case for random vectors, and a 2.06x improvement for TM classifications. With a direct, yet time-independent, design, our findings show BEA's ability to reduce inference times in more general classification hardware.
This paper describes the design, implementation, and lessons learned of the Scaledmatx One (S1) ASIC, a Machine-Learning (ML) Inference Accelerator built using an asynchronous VLSI approach. Our experience shows that a channel-based design method simplifies top-level correctness, and bundled-data implementation demonstrates benefits in power-efficiency and timing closure. We present a brief taxonomy of ML architectures (GPU, TPU, NPU), introduce the top-level architecture, modeling and design strategies, discuss its circuit architecture, and outline our tools and an execution flow that integrates open source and commercial solutions.
Static dataflow circuits are a common target for asynchronous circuit synthesis. Dataflow circuits can be implemented using fine-grained asynchronous pipelines from a variety of circuit families, typically leading to high-throughput circuit implementations. This approach has been used to design a number of different asynchronous chips including microprocessors, FPGAs, on-chip networks, and arithmetic circuits.Existing methods for translating slack elastic programs into dataflow circuits restrict the way channels can be used in an individual process; in particular, they require that a channel can only be used once per process loop iteration. We present a systematic solution to this problem that lifts this restriction, thereby enabling the translation of general slack elastic processes into dataflow components. We compare our approach with alternative strategies for this problem, and discuss why our method is better suited for high-throughput asynchronous dataflow circuit synthesis.
Nano-electromechanical switches (NEMS) are a promising chip technology for harsh environments. However, their use with conventional synchronous designs may face hurdles, as wear-out limits their number of switching cycles. In this paper we propose a novel implementation of a Muller C-Element for NEMS devices and present two case studies showing that Quasi Delay Insensitive (QDI) design can significantly decrease the number of switching cycles and thus extend the lifetime of the circuit, potentially even without an increase of the device count. Our results indicate that the benefits of QDI become more pronounced for circuits that have a high proportion of flip-flops, and in cases where slow input causes idle clock cycles. Overall, our approach of using a customized Muller C-Element in a QDI design style shows clear benefits for the considered NEMS technology.
Mount Sisyphus is the Intel Neuromorphic Computing Lab’s latest asynchronous microcontroller, first used in Loihi 2, a neuromorphic research chip. An enhanced version was fabricated and validated in Intel 3 process. It is a 32-bit integer RISC-V with multiply/divide instructions (rv32im) including an interrupt controller, real-time clock, and machine-mode features to support a real-time operating system. It has 64KB of local instruction memory and 64KB of local data memory, both ECC protected. It connects to Loihi 2’s Network-on-Chip with custom message-passing extensions and access to on-chip memory. Mount Sisyphus has moderate speed of 906 CoreMark/s and 441 CoreMark/mJ at 0.65V, but leading energy efficiency of 356 CoreMark/s and 571 CoreMark/mJ at 0.5V. Energy efficiency is enabled by asynchronous bundled-data design, pulse latches, custom SRAM, low voltage, advanced process, and architecture.
