Modern autonomous driving has widely used deep learning to process point cloud data. This application is widely deployed on embedded edge computing devices and has high security requirements. We found that backdoor attacks can pose an extremely serious threat to point cloud deep learning systems, but this attack method has not been explored in point cloud deep learning tasks. In this paper, we propose a physically implementable backdoor attack method for the point cloud deep learning model. This method can achieve good performance in the attack effect and physical realization, evaluating by preliminary experiments.
Modern embedded systems need to cater for several needs depending upon the application domain in which they are deployed. For example, mixed-critically needs to be considered for real-time and safety-critical systems and energy for battery-operated systems. At the same time, many of these systems demand for their reliability and security as well. With electronic systems being used for increasingly varying type of applications, novel challenges have emerged. For example, with the use of embedded systems in increasingly complex applications that execute tasks with varying priorities, mixed-criticality systems present unique challenges to designing reliable systems. The large design space involved in implementing cross-layer reliability in heterogeneous systems, particularly for mixed-critical systems, poses new research problems. Further, malicious security attacks on these systems pose additional extraordinary challenges in the system design. In this paper, we cover both the industry and academia perspectives of the challenges posed by these emergent aspects of system design towards designing highperformance, energy-efficient, reliable and/or secure embedded systems. We also provide our views on paths forward.
The current trend of transforming static embedded systems into open platforms (in which several software providers are able to directly load their software) drives the need to design and implement modular embedded software. Additionally, a myriad of embedded devices are expected to operate and provide services for years, or even decades, while remaining correct and secure at all times. Therefore, one of the emerging challenges for highly adaptive embedded computing platforms is to offer dynamic software composition at runtime and internal device housekeeping, which in conjunction improve device maintainability. We propose a hardware/software co-designed technique to improve both security and maintainability in modular embedded systems.
This work presents a plan for investigating transistor aging and degradation in cyber physical systems under attack. The authors discuss the importance of such concerns, particularly with regard to negative bias temperature instability, and an approach to demonstrate the adverse effects of a cyber-attack resulting in premature aging of transistors within a system's digital controllers.
Gigantic rates of data production in the era of Big Data, Internet of Thing (IoT), and Smart Cyber Physical Systems (CPS) pose incessantly escalating demands for massive data processing, storage, and transmission while continuously interacting with the physical world using edge sensors and actuators. For IoT systems, there is now a strong trend to move the intelligence from the cloud to the edge or the extreme edge (known as TinyML). Yet, this shift to edge AI systems requires to design powerful machine learning systems under very strict resource constraints. This poses a difficult design task that needs to take the complete system stack from machine learning algorithm, to model optimization and compression, to software implementation, to hardware platform and ML accelerator design into account. This paper discusses the open research challenges to achieve such a holistic Design Space Exploration for a HW/SW Co-design for Edge AI Systems and discusses the current state with three currently developed flows: one design flow for systems with tightly-coupled accelerator architectures based on RISC-V, one approach using loosely-coupled, application-specific accelerators as well as one framework that integrates software and hardware optimization techniques to built efficient Deep Neural Network (DNN) systems.
Lane detection is a challenging task in autonomous driving with strong requirements on real-time and high accuracy. Based on the theory of differential calculus, we propose a fast lane detection method for autonomous driving systems to achieve high accuracy and satisfy real-time performance. We formulate the lane differentiation to represent the lanes with a series of endpoints of line segments. A convolutional neural network is presented to predict the heatmap and the embedding vector simultaneously. The heatmap is used to represent the endpoints in lane differentiation while the embedding vector is leveraged to group endpoints into lanes. Then we implement a non-maximum suppression algorithm to combine the heatmap with the embedding vector to obtain the final lanes. Preliminary experimental results demonstrate the efficiency of our approach, which can achieve up to 43.1 times faster than traditional segmentation methods.
Buffer management is a key issue in database systems and operating systems. Recently, with the advance of machine learning, it has been a new frontier to use machine learning techniques to improve buffer management. This paper makes a preliminary study on learned buffer management, aiming to (1) present a conceptual design for learned buffer management and (2) verify whether a machine learning model can help improve the efficiency of buffer management. We first present a framework for learned buffer management, which includes a feature vector-generating Generator, a labeling Predictor, and a decision-making Replacer. Finally, we conduct a preliminary experiment on two tailor-made workloads and the results suggest the efficiency of the learned buffer manager.
It is a challenging task to resist illegal usage of Deep Neural Network (DNN) models in applications from edge computing. The existed protection method is developed based on encrypting all weights of DNN models and has achieved a promising result, which however suffers from a high computation cost. In this paper, we design a critical-weight based method to lock the DNN model to defend unauthorized usage, leading to a significant decrease in the time cost. To be specific, we analyse and figure out the critical weights of a DNN model, and then encrypt the critical weights to lock the DNN model. A set of preliminary experiments are conducted to testify the effectiveness of the proposed approach.
PREcision Timed (PRET) machines often use multithreading to achieve high CPU resources utilisation and time-determinism. Multithreading enables sharing most of the pipeline resources between threads, except the register file (RF), which is used to store thread context. Traditional multithreading on PRET machines uses large RF. We propose a register file management (RFM) technique suitable for multithreaded PRET machines, reducing the RF size. Our RFM has software-controlled RF partitions for each thread with support for runtime repartitioning. We evaluate the design on the PRET uRISC processor with a 55% average reduction of FPGA resource utilisation and show performance tradeoff on a selection of TACLeBench benchmarks.
In the field of IoT, RISC-V as an open-source instruction set shows great application potential. On the one hand, this is due to the low cost brought by the hardware open source trend. On the other hand, the modular instruction set architecture (ISA) design brings agile design ideas, and designers can pay more attention to the collaborative design of key ISA and software libraries. However, by analyzing the underlying mathematical assembly library, we found that the current RISC-V standard instruction set still has room for performance improvement for lightweight control mathematical operations. In this paper, we introduce a set of custom RISC-V ISA designs for fixed-point math libraries and perform performance evaluations to demonstrate the optimization results.
The increasing application of Machine Learning (ML) techniques in the Internet of Things (IoT) devices has led designers to leverage ML accelerators like GPGPUs in such devices. However, choosing the most appropriate accelerator for such IoT devices is very challenging as they commonly should adhere to tight constraints e.g., low power consumption, long battery lifetime, and low cost of the final products. As a consequence, designing such application-specific IoT devices becomes a non-trivial and difficult task. In this paper, we present a novel approach to estimate power consumption of CUDA-based Convolutional Neural Networks (CNNs) on GPGPUs in the design phase. Our approach is able to provide designers with an early prediction of CNNs power consumption up to an absolute error of less than 2% in comparison to the real hardware execution.
Hardware acceleration based on FPGA has been an important means to improve the computational efficiency of CNNs. However, due to the increasing complexity of the modern CNNs and the diversity of neural computing engines, it is challenging to make full use of FPGAs' customizability for efficient and fast accelerator designs. This paper proposes Wider-Frame, an automatic customization framework for building CNN accelerators on FPGA. Towards fully exploiting the customiz-ability of FPGA for specific computing scenarios, WiderFrame integrates a systematical design space exploration methodology considered with different parallel and data reuse manners among various neural computing engines, a parameterized configurable code template with a set of macro instruction mechanism, for automatically generating the underlying hardware units and the control flow. Evaluation results show that WiderFrame can well support more CNN types, and can improve the performance and the energy efficiency up to 1.25 x and 1.68 x compared with state-of-the-art frameworks.
In this paper, we propose a storage engine for MongoDB to accelerate the queries and reduce the memory usage. An FPGA-based query accelerator is deployed to speed up the queries while hot data is migrated from memory to SSD to reduce memory occupancy by our storage engine. Moreover, multiple query tasks of MongoDB are performed in parallel and query conditions are parameterized to support diversified queries. Based on TPC- H benchmark and Tencent data set, experimental results demonstrate that our storage engine can achieve higher query efficiency (saving up to 63.5 % time overhead) and lower memory occupancy (reducing up to 73.4 % memory usage) compared with traditional MongoDB.
The role of unmanned vehicles for searching and localizing the victims in disaster impacted areas such as earthquake-struck zones is getting more important. Self-navigation on an earthquake zone has a unique challenge of detecting irregularly shaped obstacles such as cracks, puddles, and debris on the streets. In this paper, we present an edge-based self-navigation vehicle that can detect unique obstacles in earthquake-struck sites and discuss the performance and energy impact of various neural network structures, edge platforms, and optimizations. To enable vehicles to safely navigate earthquake-struck sites, we compiled a new image database of various earthquake impacted regions and developed semantic segmentation models that identify obstacles unique to earthquake-sites. The models are tested on an edge-based car platform. To our best knowledge, this is the first study that identifies unique challenges and discusses the performance and energy impact of edge-based self-navigation vehicles for earthquake-struck zones.
In this paper, we propose a new Hardware Trojan Design. This design makes all HT trigger inputs have the same impact as functional inputs on output signals. It is difficult to distinguish between trigger inputs and functional inputs. Simultaneously, trigger inputs will not be identified as redundant inputs. This approach can defeat the existing detection methods which identify weakly-affecting and redundant trigger inputs across multiple sequential levels. The proposed HT has stealthiness and general applicability.
High-level synthesis entails application of a sequence of transformations to compile a high-level description of a hardware design (e.g., in C/C++/SystemC) into a register-transfer level (RTL) implementation. However, an error may exist in the RTL implementation from the compiler in the high-level synthesis due to the complex and error prone compiling process. Global common subexpression elimination (GCSE) is a commonly used code motion technique in the scheduling of high-level synthesis. In this paper, we present an equivalence checking method to verify GCSE in the scheduling of high-level synthesis by enhancing the path equivalence criteria. The initial experimental results demonstrate our method can indeed verify the GCSE which has not been properly addressed in the past.
Current LSM-Tree-based blockchain storage system will assign the data from multiple system users to the same disk drive. This will lead to the inefficient usage of physical spaces in disk and cause extra compaction operations for LSM - Tree. This paper presents Meta-Chain , a user-aware cross-layer space allocation strategy for blockchain storage systems. As a cross-layer design, Meta-Chain redesigns the organization of LSM - Tree and utilizes the rich functionalities provided by open-channel SSD. Experimental results show that Meta-Chain can effectively reduce write amplification and extend the lifetime of SSD in comparison with representative schemes.
The Capsule Networks (CapsNets) is an advanced form of Convolutional Neural Network (CNN), capable of learning spatial relations and being invariant to transformations. CapsNets requires complex matrix operations which current accelerators are not optimized for, concerning both training and inference passes. Current state-of-the-art simulators and design space exploration (DSE) tools for DNN hardware neglect the modeling of training operations, while requiring long exploration times that slow down the complete design flow. These impediments restrict the real-world applications of CapsNets (e.g., autonomous driving and robotics) as well as the further development of DNNs in life-long learning scenarios that require training on low-power embedded devices. Towards this, we present XploreDL , a novel framework to perform fast yet high-fidelity DSE for both inference and training accelerators, supporting both CNNs and CapsNets operations. XploreDL enables a resource-efficient DSE for accelerators, focusing on power, area, and latency, highlighting Pareto-optimal solutions which can be a green-lit to expedite the design flow. XploreDL can reach the same fidelity as ARM's SCALE-sim, while providing 600x speedup and having a 50x lower memory-footprint. Preliminary results with a deep CapsNet model on MNIST for training accelerators show promising Pareto-optimal architectures with up to 0.4 TOPS/squared-mm and 800 fJ/op efficiency. With inference accelerators for AlexNet the Pareto-optimal solutions reach up to 1.8 TOPS/squared-mm and 200 fJ/op efficiency.
It is a challenging task to resist adversarial attacks due to the imperceptibility of adversarial examples. The passive defense method is developed based on a series of input transformations and has achieved a promising result, which however suffers from a high computation cost. In this paper, we design a new heatmap-aware method to defend adversarial attacks, leading to a significant decrease in the time cost. To be specific, we compute the classification importance from each part of the input to obtain the heatmap of the data, and the key areas of classification are extracted according to the heatmap. A series of transformations are applied to the key areas of the classification, which reduces the amount of data to be processed and thus reduces the time cost. A set of preliminary experiments are conducted to testify the effectiveness of the proposed approach.
SSD has been widely deployed in data centers to provide low access latency with high throughput for large-scale RDF storage system. When performing data query on SSDs, the RDF -based graph data may be sequentially read multiple times due to the semantic gap between the graph and SSD structures. In this paper, we propose a scheme called GraphPage to bridge the semantic gap between RDF graph and SSD. GraphPage partitions the RDF graph into small graphs and directly maps these small graphs into the flash pages. To achieve this, we first expose the internal page organization by redesigning an SSD. By exploring the page-level graph store, we can efficiently reduce the page access times inside SSDs, thus significantly enhancing the query efficiency. We conduct experiments on a real hardware platform. Extensive experiments on synthetic and real datasets show that the proposed strategy improves the performance of data query by more than two times.
