This paper introduces two novel techniques, TDMEN-CACHE and TDMEN-INTERSEC, designed to enhance load balancing and energy efficiency in Wireless Multimedia Sensor Networks (WMSNs). These techniques leverage temporal and spatial redundancies to optimize task division among sensor nodes, reducing energy consumption and extending network lifetime. TDMEN-CACHE minimizes reprocessing by utilizing cached data from previous multimedia events, while TDMEN-INTERSEC capitalizes on overlapping sensing areas to distribute processing tasks among neighboring nodes. The proposed methods were evaluated using real-world case studies in precision agriculture and bird monitoring, demonstrating significant improvements in energy efficiency, event detection rates, and network longevity compared to conventional solutions. A packet loss model was also integrated to simulate real-world communication scenarios, further validating the robustness of the techniques under varying conditions.
Multi-core embedded systems face increasing pressure to guarantee timing predictability while sharing critical hardware resources such as caches and memory buses. Although static partitioning hypervisors provide strong spatial isolation, they do not alone prevent temporal interference caused by concurrent memory accesses. To address this gap, this work integrates a fine-grained memory bandwidth regulation mechanism into the Bao hypervisor, extending the MemGuard framework with distinct accounting for read and write operations. Treating memory accesses asymmetrically enables more accurate budgeting and avoids the conservatism inherent in uniform regulation, improving both resource utilization and isolation. The system enforces dedicated bandwidth guarantees and dynamically reallocates unused quotas via feedback-driven budget functions, making it suitable for mixed-criticality environments where high-priority tasks demand strict timing consistency. The implementation is evaluated on a quad-core ARMv8 platform (Raspberry Pi 4) running multiple Bao partitions, each executing periodic real-time tasks alongside memory-intensive workloads. Experiments compare several adaptive budget policies and reveal that separating read and write regulation reduces interference and enhances predictability without sacrificing throughput. Among the evaluated approaches, Adaptive Memory Budget with Penalty (AMBP) demonstrated strong scalability, while Adaptive Feedback Control (AFC) and Proportional-Integral Controller (PIC) achieved an advantageous balance between performance stability and computational overhead. Overall, the integration advances memory isolation capabilities for lightweight hypervisors and provides an efficient foundation for reliable real-time execution on modern embedded multi-core platforms.
In the realm of human–computer interaction, convolutional neural networks (CNN) have recently gained increasing attention for solving hand gesture recognition problems. Numerous existing CNN-based architectures perform well with recognition accuracy but may result in high computational complexity and require excessive resources when deployed on embedded devices. In this paper, an efficient hardware accelerator based on Tiny YOLOv2 networks using binary weights and low-bit activations is proposed to address the above issue. The processing elements (PEs) are designed to leverage low-bit calculations and resource allocation is employed to improve hardware performance. Furthermore, the design space of an accelerator is explored by fine-tuning parameters such as parallelization factors and clock rates. Experiments conducted on the PASCAL VOC and Hindi Indian Sign Language (ISL) datasets demonstrate that the Tiny YOLOv2 model with 1-bit weights and 5-bit activations achieves impressive mean average precision (mAP) scores of 50.2
In developing resource-constrained Internet of Things applications, the focus on design and modeling supports embedded programming. Taking into account the specificities of the application and the limitations of resource-constrained devices in the design and modeling process will streamline the development process. Traditional solutions aimed at resource-constrained devices often focus on programming at the expense of design and modeling, compromising systems with potential flaws and leading to rework. This paper tackles the challenge of developing programs for resource-constrained IoT devices by proposing a statechart-based design and modeling approach. Statecharts offer a powerful and accessible solution for event-driven IoT applications due to their compact visual representation of reactive systems. The intuitive visualization of state transitions and event-driven logic aligns seamlessly with the core event-driven behaviors of IoT devices. Statechart4IoT, as the implementation of this approach, offers a compelling solution for designing, modeling, and pre-implementation analysis of resource-constrained IoT applications. Leveraging the statechart formalism oriented to resource-constrained embedded environments, this framework provides an intuitive web-based environment that enables developers to design and model IoT applications in an interactive visual programming manner. Finally, the framework generates binary-based statechart scripts with small footprints optimized for deployment to resource-constrained devices. To fully realize the capabilities of the proposed approach, a statechart interpreter solution can be implemented as middleware on devices. This will enable the execution of deployed scripts, which ultimately complete the computational behavior of statecharts. This paper evaluates our approach with such a statechart middleware on two distinct operating systems and three hardware platforms. The results obtained indicate the feasibility of the proposed approach.
This study employs physics-informed neural ordinary differential equations to perform time series forecasting for dynamic system monitoring. In this approach, predictions of the system’s dynamic response over time are generated by integrating physical laws with observed data, enhancing forecasting accuracy. The dataset consists of vibration data from radial and tangential accelerometers, recorded over a 5-second interval under various conditions such as faults, imbalances, and misalignments. The results reveal that the fully informed forecasting model consistently produces lower kurtosis values and a more normally distributed error, suggesting superior model generalization over time. Meanwhile, the partially informed model also shows improved performance, with fewer biased predictions than the uninformed model, which exhibits higher kurtosis and a greater number of outliers in its forecasts. Importantly, the study demonstrates that the model can successfully extrapolate system behavior beyond the training period, maintaining high prediction accuracy despite the limited amount of data. Overall, these findings underscore the potential of using Physics-Informed Neural Ordinary Differential Equations for reliable time series forecasting in dynamic system monitoring.
The advent of manycore systems has led to the need for efficient dynamic thermal and reliability management techniques to increase system reliability. Increasing power density and thermal hotspots in manycore systems pose significant challenges to reliability and performance. Existing techniques often fail to scale effectively or consider long-term reliability impacts. This work aims to develop a lightweight and scalable management strategy for manycore systems that integrates dynamic thermal management and dynamic reliability management using application mapping and task migration. The primary contribution is the introduction of the Failure In Time (FIT)-aware Learning Heuristic for Application Allocation (FLEA), which leverages Q-learning to optimize task allocation and migration based on FIT monitoring. FLEA operates in two phases: a design phase that uses Q-learning to train a policy table (Q-table) and a runtime phase that utilizes this Q-table to make decisions on task allocation and migration. The Q-table is populated with values representing the best task deployment patterns, minimizing thermal hotspots and maximizing system reliability. The evaluation of FLEA demonstrates improvements over state-of-the-art techniques. FLEA effectively reduces the thermal amplitude, peak temperature, and spatial thermal distribution, resulting in enhanced Mean Time To Failure for the system.
Edge computing is increasingly important in the embedded domain as it improves latency, security, and energy efficiency. However, edge devices are often constrained by power budgets that limit achievable performance; thus improving energy efficiency is essential to achieve maximum performance under power constraints. An effective way of improving energy efficiency is the adoption microprocessors operating at Near-Threshold Voltage (NTV). Unfortunately, this comes with reduced frequency and increased process variations that must be harnessed. To address these challenges, we propose a two-step design methodology (design- and post-design time) for heterogeneous edge-based computing systems with NTV while effectively managing variations. Our methodology results in better-performing Multi-Processor Systems-on-Chip composed of a blend of cores at NTV or nominal voltages within a given power limit. Firstly, we propose a sampling-based methodology that enables variation-aware design exploration during the design stage. Secondly, we introduce an efficient post-design frequency scaling strategy to reduce power dissipation or improve system performance if possible. We evaluate our methodology using RISC-V heterogeneous cores and demonstrate that careful variation-aware design exploration can improve system performance by 52% on average compared to variation-unaware designs. Additionally, our methodology achieves a 12% improvement compared to variation-aware conventional designs that operate fully at nominal voltage.
With the modernization of the automotive industry, a large amount of data is generated by vehicles during operation. When interpreted analytically, it can result in advances in several areas, such as safety, durability, production efficiency, fuel consumption, and gas emissions. In this work, we focus on engine torque and its regression, to enable the understanding of its behavior and help improve the performance of engines and vehicles, mainly in product development and testing. In addition, it highlights the relationship between torque and misfire for optimizing engine components by showing their impacts, as it is a common failure in combustion engines that impairs engine performance. After a rigorous process of feature selection relevant to torque, we collect data directly from a vehicle’s ECU to train and evaluate machine learning algorithms to perform torque regression without relying on synthetic data or public datasets, using misfire detection as one of the inputs to the algorithms. In a car that reaches a torque of 144 Nm, our results reached up to an RMSE of 3.3830 (Nm) ^2 , MAE of 2.1620 (Nm), and R ^2 of 0.99. Furthermore, our methodology acquired and processed data in real-time at a cloud server, that detects faults and calculates torque with the vehicle in motion, using less computationally demanding algorithms. These findings not only highlight our ability to predict the engine’s torque and its relation with misfires but also our competence in analyzing additional parameters essential to vehicle performance.
To improve the energy efficiency of computation, accelerators trade off performance and energy consumption for flexibility. Fixed-function accelerators reach high energy efficiency, but are inflexible. Adding programmability via an instruction set architecture (ISA) incurs an energy consumption overhead, as instructions are fetched and decoded. To reduce it, hardware-controlled instruction caches and software-controlled components, such as loop buffers and (programmable) dictionaries improve the energy efficiency of instruction streams in embedded processors. Reducing the instruction overhead with code compression is well established and dictionary compression has been an effective approach due to its simplicity. Compared to static dictionaries, adding programmability improves the effectiveness. However, run-time-programmable dictionary compression and its effect on energy consumption has not been thoroughly studied. We describe a scheme to target energy efficiency by using fine-grained programmable dictionaries in embedded compute devices. Guided by compile-time analysis, the dictionary contents are changed during execution. On CHStone and Embench suites, our method reduces energy consumption on average by 11.4
Human Activity Recognition (HAR) is an important area of research due to its applications in health monitoring, elderly care, and personal fitness tracking. The challenge is deploying efficient and accurate HAR systems on resource-constrained and/or battery-powered embedded devices, which require low power consumption and processing efficiency. This work optimizes a Convolutional Neural Network (CNN) model for HAR, targeting resource-constrained and battery-powered processors. This CNN model uses accelerometer and gyroscope data from 6 people performing five actions, with sensor readings taken from four positions. The goal is to balance accuracy, performance, and power consumption for real-world deployment in wearable devices. Key contributions include introducing an Extended 1D CNN model that enhances temporal awareness and accuracy without the overhead of floating-point computations, evaluating and applying quantization methods to minimize model size with minimal accuracy loss, and assessing the model’s performance on a RISC-V processor. Results show an accuracy increase from 74
With the increase in the non-linearity and complexity of the driving system’s environment, developing and optimizing related applications is becoming more crucial and remains an open challenge for researchers and automotive companies alike. Model predictive control (MPC) is a well-known classic control strategy used to solve online optimization problems. MPC is computationally expensive and resource-consuming. Recently, machine learning has become an effective alternative to classical control systems. This paper provides a developed deep neural network (DNN)-based control strategy for automated steering deployed on FPGA. The DNN model was designed and trained based on the behavior of the traditional MPC controller. The performance of the DNN model is evaluated compared to the performance of the designed MPC which already proved its merit in automated driving task. A new automatic intellectual property generator based on the Xilinx system generator (XSG) has been developed, not only to perform the deployment but also to optimize it. The performance was evaluated based on the ability of the controllers to drive the lateral deviation and yaw angle of the vehicle to be as close as possible to zero. The DNN model was implemented on FPGA using two different data types, fixed-point and floating-point, in order to evaluate the efficiency in the terms of performance and resource consumption. The obtained results show that the suggested DNN model provided a satisfactory performance and successfully imitated the behavior of the traditional MPC with a very small root mean square error (RMSE = 0.011228 rad). Additionally, the results show that the deployments using fixed-point data greatly reduced resource consumption compared to the floating-point data type while maintaining satisfactory performance and meeting the safety conditions
Simulations are key steps in the design, implementation, and verification of autonomous vehicles (AV). Parallel to this, typical simulation tools fail to integrate the entirety of the aspects related to the complexity of AV applications, such as data communication delay, security, and the integration of software/hardware-in-the-loop and other simulation tools. This work proposes a SmartData-based middleware to integrate AV simulators and external tools. The interface models the data used on a simulator and creates an intermediary layer between the simulator and the external tools by defining the inputs and outputs as SmartData. A message bus is used for communication between SmartData following their Interest relations. Messages are exchanged following a specific protocol. Nevertheless, the architecture presented is agnostic of protocol. Moreover, we present a data-centric AV design integrated into the middleware. The design considers the standardization of the data interfaces between AV components, including sensing, perception, planning, decision, and actuation. Therefore, the presented design promotes a transparent integration of the AV simulation with other simulators (e.g., network simulators), cloud services, fault injection mechanisms, digital twins, and hardware-in-the-loop scenarios. Moreover, the design allows for transparent, runtime component replacement and time synchronization, the modularization of the vehicle components, and the addition of security aspects in the simulation. We present a case-study application with an AV simulation using CARLA, and we measure the end-to-end delay and overhead incurred in the simulation by our middleware. An increase in the end-to-end delay was measured once data communication was not acknowledged in the original scenario, and data was assumed to be ready for processing with no communication delay between sensors, decision-making, and actuation units.
Internet of Things (IoT) devices produce massive amounts of data in a very short time. Transferring these data to the cloud to be analyzed may be prohibitive for applications that require near real-time processing. One solution to meet such timing requirements is to bring most data processing closer to IoT devices (i.e., to the edge). In this context, the present work proposes a distributed architecture that meets the timing requirements imposed by Industrial IoT (IIoT) applications that need to apply Machine Learning (ML) models with high accuracy and low latency. This is done by dividing the tasks of storing and processing data into different layers—mist, fog, and cloud—using the cloud layer only for the tasks related to long-term storage of summarized data and hosting of necessary reports and dashboards. The proposed architecture employs ML inferences in the edge layer in a distributed fashion, where each edge node is either responsible for applying a different ML technique or the same technique but with a different training data set. Then, a consensus algorithm takes the ML inference results from the edge nodes to decide the result of the inference, thus improving the system’s overall accuracy. Results obtained with two different data sets show that the proposed approach can improve the accuracy of the ML models without significantly compromising the response time.
Large-scale attacks on IoT and edge computing devices pose a significant threat. As a prominent example, Mirai is an IoT botnet with 600,000 infected devices around the globe, capable of conducting effective and targeted DDoS attacks on (critical) infrastructure. Driven by the substantial impacts of attacks, manufacturers and system integrators propose Trusted Execution Environments (TEEs) that have gained significant importance recently. TEEs offer an execution environment to run small portions of code isolated from the rest of the system, even if the operating system is compromised. In this publication, we examine TEEs in the context of system monitoring and introduce the Trusted Monitor (TM), a novel anomaly detection system that runs within a TEE. The TM continuously profiles the system using hardware performance counters and utilizes an application-specific machine-learning model for anomaly detection. In our evaluation, we demonstrate that the TM accurately classifies 86% of 183 tested workloads, with an overhead of less than 2%. Notably, we show that a real-world kernel-level rootkit has observable effects on performance counters, allowing the TM to detect it. Major parts of the TM are implemented in the Rust programming language, eliminating common security-critical programming errors.
Coarse-grain reconfigurable architectures, which provide high computing throughput, low cost, scalability, and energy efficiency, have grown in popularity in recent years. SiLago is a new VLSI design framework comprised of two coarse-grain reconfigurable fabrics: a dynamically reconfigurable resource array and a distributed memory architecture. It employs the Vesyla compiler to map streaming applications on these fabrics. Binding is a critical step in the high-level synthesis that maps operations and variables to functional units and storage elements in the design. It influences design performance metrics such as power, latency, area, etc. The current version of Vesyla does not support automatic binding, and it has to be specified manually through pragmas, which makes it less flexible. This paper proposes various approaches to automate the binding in Vesyla. We present a list scheduling-based approach to automate functional unit binding and an integer linear programming approach to automate register binding. Furthermore, we determine the binding of various basic linear algebraic subprogram and image processing tasks using the proposed approaches. Finally, a comparative analysis has been made between the automatic and manual binding concerning the power dissipation and latency for various benchmarks. The experimental results show that the proposed automatic binding consumes significantly less power for nearly the same latency as manual binding.
There is a high energy cost associated with training Deep Neural Networks (DNNs). Off-chip memory access contributes a major portion to the overall energy consumption. Reduction in the number of off-chip memory transactions can be achieved by quantizing the data words to low data bit-width (E.g., 8-bit). However, low-bit-width data formats suffer from a limited dynamic range, resulting in reduced accuracy. In this paper, a novel 8-bit Floating Point (FP8) data format quantized DNN training methodology is presented, which adapts to the required dynamic range on-the-fly. Our methodology relies on varying the bias values of FP8 format to fit the dynamic range to the required range of DNN parameters and input feature maps. The range fitting during the training is adaptively performed by an online statistical analysis hardware unit without stalling the computation units or its data accesses. Our approach is compatible with any DNN compute cores without any major modifications to the architecture. We propose to integrate the new FP8 quantization unit in the memory controller. The FP32 data from the compute core are converted to FP8 in the memory controller before writing to the DRAM and converted back after reading the data from DRAM. Our results show that the DRAM access energy is reduced by 3.07 × while using an 8-bit data format instead of using 32-bit. The accuracy loss of the proposed methodology with 8-bit quantized training is ≈ 1% for various networks with image and natural language processing datasets.
Among the numerous benefits that novel RRAM devices offer over conventional memory technologies is an inherent resilience to the effects of radiation. Hence, they appear suitable for use as a memory subsystem in a computer architecture for satellites. In addition to memory devices resistant to radiation, the concept of applying protective measures dynamically promises a system with low susceptibility to errors during radiation events, while also ensuring efficient performance in the absence of radiation events. This paper presents the first RRAM-based memory subsystem for satellites with a dynamic response to radiation events. We integrate this subsystem into a computing platform that employs the same dynamic principles for its processing system and implements modules for timely detection and even prediction of radiation events. To determine which protection mechanism is optimal, we examine various approaches and simulate the probability of errors in memory. Additionally, we are studying the impact on the overall system by investigating different software algorithms and their radiation robustness requirements using a fault injection simulation. Finally, we propose a potential implementation of the dynamic RRAM-based memory subsystem that includes different levels of protection and can be used for real applications in satellites.
The present research work proposes an energy efficient diagonal mesh based topology called DiamondMesh. By introducing diagonal links into the baseline mesh topology, the proposed DiamondMesh improves network performance while retaining the regular, simple and scalable properties of the Mesh topology. Topological properties of DiamondMesh have been explored and compared with that of other competitive diagonal mesh topologies. With the help of Booksim2.0 simulator, the proposed topology has been evaluated under a variety of traffic patterns and the results have been compared to those obtained with Mesh and the existing diagonal mesh topologies. The proposed topology and other considered topologies have been synthesised using xilinx vivado design compiler and the results have been analysed. The evaluation results show that there has been a significant reduction of latency compared to Mesh and other diagonal mesh topologies except DMesh and a considerable reduction of area and power compared to the DMesh topology. Thus, DiamondMesh establishes to be a highly efficient diagonal mesh-based topology for a variety of applications.
Fail-operational behavior of safety-critical software for autonomous driving is essential as there is no driver available as a backup solution. In a failure scenario, safety-critical tasks can be restarted on other available hardware resources. Here, graceful degradation can be used as a cost-efficient solution where hardware resources are redistributed from non-critical to safety-critical tasks at run-time. We allow non-critical tasks to actively use resources that are reserved as a backup for critical tasks, which would be otherwise unused and which are only required in a failure scenario. However, in such a scenario, it is of paramount importance to achieve a predictable timing behavior of safety-critical applications to allow a safe operation. Here, it has to be ensured that even after the restart of safety-critical tasks a guarantee on execution times can be given. In this paper, we propose a graceful degradation approach using composable scheduling. We use our approach to present, for the first time, a performance analysis which is able to analyze timing constraints of fail-operational distributed applications using graceful degradation. Our method can verify that even during a critical Electronic Control Unit failure, there is always a backup solution available which adheres to end-to-end timing constraints. Furthermore, we present a dynamic decentralized mapping procedure which performs constraint solving at run-time using our analytical approach combined with a backtracking algorithm. We evaluate our approach by comparing mapping success rates to state-of-the-art approaches such as active redundancy and an approach based on resource availability. In our experimental setup our graceful degradation approach can fit about double the number of critical applications on the same architecture compared to an active redundancy approach. Combined, our approaches enable, for the first time, a dynamic and fail-operational behavior of gracefully degrading automotive systems with cost-efficient backup solutions for safety-critical applications.
Evaluating the effectiveness of system scheduling and energy savings in embedded real-time systems with low-computing resources is the problem addressed in this paper. In such systems, the characteristics of the implemented scheduling policy play a relevant role in both schedulability and energy consumption. Ideally, the scheduling policy should provide higher schedulability bounds and low runtime overheads, allowing for better usage of available slack in the schedule for energy saving purposes. Due its low overhead and simple implementation, the usual scheduling policy employed in real-time embedded systems is based on fixed priority scheduling (FPS). Under this scheme, as the priority of all system tasks are assigned at design time, a simple priority vector suffices to indicate the current ready task to run. System schedulability, however, is usually lower than that provided by dynamic priority scheduling (DPS) according to which task priorities are assigned at runtime. Managing dynamic priority queues incurs higher overheads, though. Deciding whether DPS is a viable choice for such embedded systems requires careful evaluation. We evaluate two implementations of Earliest Deadline First (EDF), a classical DPS policy, implemented in FreeRTOS running on an ARM-M4 architecture. EDF is compared against an optimal FPS, namely Rate-Monotonic (RM). Further, two mechanisms for energy savings are described. They differ by the manner they compute the slack available in an EDF schedule, statically (SS-EDF) or dynamically (DS-EDF). These two approaches are experimentally evaluated. Results indicate that EDF can be effectively used for energy savings.
