Hardware verification is a critical stage in the design flow, ensuring functional correctness and reliability of increasingly complex systems. Traditional verification methodologies, such as simulation- and formal-based approaches, suffer from limited scalability, high manual effort, and growing state-space explosion as design complexity increases. Recent advances in large language models (LLMs) have enabled their adoption for verification-related tasks such as testbench generation, assertions, security properties, and bug localization. However, existing LLMbased verification flows face significant limitations, including context-size constraints, lack of reasoning, and poor scalability across abstraction levels. To address these challenges, agentic workflows have emerged as a promising paradigm that orchestrates LLMs through structured reasoning, interfacing with toolflows and feedback loops. In this work, we provide a systematic assessment of current agentic LLM workflows for hardware verification, analyzing their practicality and limitations. Furthermore, we propose a novel LLM-based agentic framework that enhances verification effectiveness across RTL and gatelevel abstractions. We demonstrate the potential of the proposed frameworks through evaluation on six open-source benchmarks, showing accuracy, coverage and speedup improvements.
Recent advancements in Large Language Models (LLMs) have demonstrated their growing capability to generate complex Register-Transfer Level (RTL) designs, including hardware accelerators for Post-Quantum Cryptography (PQC) primitives. However, hardware implementations of cryptographic algorithms demand more than just functional correctness and optimal performance; they must also offer resilience against sidechannel attacks (SCAs). For the first time in the literature, we explore the potential of LLMs to automate the generation of SCA-resilient RTL. We focus on the Number Theoretic Transform (NTT) operation in CRYSTALS-Kyber NIST standard for MLKEM, a critical cryptographic component known to be vulnerable to SCAs, mainly because of the constrained sample space of the key parameters used in these algorithms. By guiding the LLM to incorporate countermeasures during the design phase, this study aims to streamline the development of secure, next-generation cryptographic hardware.
As large language models (LLMs) are increasingly fine-tuned for hardware tasks like RTL code generation, the scarcity of high-quality datasets often leads to the use of rapidly assembled or generated training data. These datasets frequently lack security verification and are highly susceptible to data poisoning attacks. Such poisoning can cause models to generate syntactically valid but insecure hardware modules that bypass standard functionality checks. To address this, we present SafeTune, a framework designed to harden LLM-based RTL generation against poisoning, specifically focusing on hardware Trojan (HT) insertion. SafeTune integrates two core components: (i) a Graph Neural Network (GNN) that models structural properties to identify anomalous circuitry patterns during fine-tuning, and (ii) a semantic verification module using text embeddings and an XGBoost classifier to assess prompt security. By coupling structural and semantic knowledge, SafeTune effectively filters poisoned inputs without sacrificing legitimate data. Experimental results demonstrate that SafeTune significantly enhances the robustness and reliability of LLM fine-tuning without requiring modifications to the underlying model architecture.
SystemVerilog Assertions (SVA) are essential for formal verification of digital hardware, yet their manual creation demands significant expertise in both the design under verification and temporal logic. Recent studies have explored using large language models (LLMs) to automate SVA generation, but existing approaches suffer from incorrect signal references, missing timing constraints, and lack of formal correctness guarantees. This paper presents ProofLoop, a tool-augmented ReAct agent that generates SVA from natural-language specifications using a solver-in-the-loop approach. The agent operates in two phases: Phase A autonomously gathers design context by invoking EDA and formal tools, including semantic search over an AST-indexed vector database and JasperGold structural queries, while Phase B generates SVA and iteratively refines it using JasperGold formal proof feedback over up to fixed (here 3) verification rounds. We evaluate ProofLoop on FVEval Design2SVA design benchmarks and demonstrate that this framework can achieve 93.7
The globalization of integrated circuit (IC) design and manufacturing has increased the exposure of hardware intellectual property (IP) to untrusted stages of the supply chain, raising concerns about reverse engineering, piracy, tampering, and overbuilding. Hardware netlist obfuscation is a promising countermeasure, but automating the generation of functionally correct and security-relevant obfuscated circuits remains challenging, particularly for benchmark-scale designs. This paper presents an agentic, large language model (LLM)-driven framework for automated hardware netlist obfuscation. The proposed framework combines retrieval-grounded planning, structured lock-plan generation, deterministic netlist compilation, functional verification, and SAT-based security evaluation. Rather than a single prompt-to-output generation step, the framework decomposes the task into specialized stages for circuit analysis, synthesis, verification, and attack evaluation. We evaluate the framework on ISCAS-85 benchmarks using functional equivalence checking and SAT-based attacks. Results show that the framework generates correct locked netlists while introducing measurable output corruption under incorrect keys, while SAT attacks remain effective. These findings highlight both the potential and current limitations of agentic LLM-driven obfuscation.
Arbiter-based Physically Unclonable Functions (APUFs) utilize the variability in manufacturing to create distinct digital identifiers for integrated circuits (ICs). Essentially, the input-output functions / truth-tables / full set of "responses" to "challenges", serve as potential hardware security primitives. To fulfill this role, every APUF batch from the same design should exhibit specific features; two of the most important are the response bias and uniqueness. A faulty APUF batch with a mu-fault from the design phase fails to achieve desired uniqueness levels and sometimes exhibits undesired response bias as well, hence is unqualified for security purposes. Instead of discarding such faulty APUFs and re-designing, we present a novel method to salvage a faulty APUF batch with the presence of multiple mu-faults, so that the desired uniqueness and bias are restored. This is done by carefully selecting challenges that can mitigate the impact of the faults. Such a salvaging strategy via challenge selection is intrinsically difficult, due to the enormous size of the challenge set, the black-box nature of APUFs, and the need to perform such tasks efficiently. To overcome these problems, we propose a simple yet effective way to estimate the intensity of the multiple faults and use them to guide the challenge selection process. The proposed method can efficiently find large challenge sets that achieve the desired response bias and uniqueness, thus salvaging a faulty APUF batch in the post-production phase.
Compute-in-Memory (CiM) architectures, particularly those leveraging SRAM-based arrays, present significant opportunities for accelerating deep learning by mitigating data movement bottlenecks in traditional von Neumann systems. SRAM-based CiM offers notable advantages, including speed, seamless CMOS integration, and compatibility with existing System-on-Chip (SoC) designs. However, challenges persist, primarily stemming from analog-domain computations that necessitate analog-to-digital (A/D) and digital-to-analog (D/A) conversions, leading to reduced accuracy, increased power overhead, and rigid operational constraints. To overcome these limitations, we propose MOSAIC, a novel CiM architecture designed around three foundational principles: (1) co-designing deep learning operators for CiM such as employing multiplication-free computations and frequency-domain processing to minimize/eliminate DAC/ADC overheads; (2) leveraging a memory-immersed digitization approach that utilizes parasitic bit-lines as capacitive DACs within CiM arrays, thereby significantly reducing peripheral complexity and enhancing scalability; and (3) orchestrating inference over a network of compact CiM mu Arrays by dynamically interconnecting them to provide flexibility, efficiency, and minimized computational overhead for varied inference workload characteristics. Collectively with these fundamental innovations, MOSAIC addresses critical bottlenecks in accuracy, scalability, and flexibility, unlocking CiM's full potential for efficient deep learning in embedded systems.
Modern computing systems rely on System-on-Chips (SoCs) to integrate multiple Intellectual Property (IP) cores developed in-house or acquired from third-party vendors with varying trust levels. Commercial Off-The-Shelf (COTS) components, such as microcontrollers and FPGAs, offer ready-made solutions but introduce security risks, especially in an untrusted supply chain. Effective verification of both IP cores and COTS components is essential for ensuring functionality, security, and reliability. Traditional IP verification techniques are often complex and error-prone due to over-reliance on manual efforts, while COTS verification poses significant challenges due to their inherent black-box nature and diverse integrity issues. The emergence of Large Language Models (LLMs) significantly enhances hardware verification by automating tasks such as code generation and bug fixing. In this paper, we present a review of LLM-based IP verification methods and discuss challenges in current verification practices. Next, we propose an LLM-driven workflow that generates test programs for COTS verification and demonstrate its effectiveness through experimental analysis on open-source COTS processors.
In safety-critical applications such as biomedical and automotive electronics, soft errors induced by radiation particles pose a significant reliability concern. This paper presents a novel Filtering Buffer-based D Flip-Flop (FB-DFF) designed to enhance radiation hardening while minimizing area and timing overheads. The FB-DFF integrates a Filtering Buffer (FB) and an Auto Delay Element (ADE) to effectively filter out transient errors and ensure the correct input signal is latched. The Single-Master Dual-Slaves (SMDS) architecture further prevents error propagation to the output. Experimental results demonstrate that FB-DFF can resist radiation particles below 77 LET, providing full protection against both Single Event Transient (SET) and Single Event Upset (SEU). Compared to existing designs, FB-DFF reduces area overhead by 44% and timing overhead by 144% at the chip level, making it a highly efficient solution for radiation-hardened applications. The proposed FB-DFF offers a balanced trade-off between radiation hardening capability, area, and timing performance, making it suitable for integration into various safety-critical systems.
Performing scan test failure diagnosis is necessary for advanced semiconductor manufacturing technologies to improve yield. A pre-silicon diagnosis simulation is essential to avoid low diagnosis resolution during volume production. Like fault simulation to identify test quality problems, diagnosis simulation identifies diagnosis quality problems. The issues can be classified into three areas: (1) Failing data collected from the automatic test equipment (ATE) is insufficient for diagnosis. To fix this problem, ATE needs to use larger fail data storage; (2) Production scan test patterns are not adequate for diagnosis, such that better test pattern selection or new diagnosis-specific test patterns should be used; (3) Designs are not friendly for diagnosis, so design-for-diagnosis enhancements should be used.A fault dictionary with complete failing bit information on all faults can be used for diagnosis simulation. However, a fault dictionary requires lots of memory to store the failing bits and a long time to query the dictionary. We propose using an Asymmetric Partition Tree (APT) to extract the information stored in a fault dictionary for diagnosis simulation usage. APT can be used to calculate diagnosis coverage and analyze the impact of ATE failed data storage limit on diagnosis coverage with and without ATE pin-based storage limit. The information stored in APT also benefits other applications, such as diagnosis pattern sampling. APT can be proven to have the minimum tree size for diagnosis simulation.
Integration of analog and RF circuits with advanced node digital systems has leapfrogged analog circuits by several technology nodes. This has resulted in higher defect rates as well as higher process variations. Another point of pressure is that some application domains, such as the automotive industry, require very low defect rates. To ensure that the circuits are thoroughly tested without increasing the test cost severely, test optimization methods can be applied. Examples of test optimization can include the use of alternate tests, reduced test sets, and built-in self-tests. Defect coverage of the optimized tests needs to be evaluated to ensure high-quality products. For analog circuits, defect definitions are generally continuous and minimum detectable deviation (of hard and soft defects) may differ from one test to another. Finding this detectability point is important to compare potential test conditions. In this paper, we propose an algorithm to determine the minimum detectable defect severity for each defect under given test conditions. Ultimately, this information can be used to find the most sensitive test method that already covers the detection limit of other methods. Experiments on an 8-bit ADC circuit show that the proposed algorithm finds the defect detectability limits of different test methods in only a few search steps and yields accurate results.
The increasing complexity of electronic systems in autonomous electric vehicles necessitates robust methods for forecasting the degradation of critical components such as printed circuit boards (PCBs). Various time series forecasting methods have been investigated to predict in-situ resistance degradation under vibration loads. However, these methods failed to capture the degradation trend under strong measurement noise. This paper introduces Monotonic Segmented Linear Regression (MSLR), a novel approach designed to capture monotonic degradation trends in time series data under significant measurement noise. By incorporating monotonic constraints, MSLR effectively models the non-decreasing behavior characteristic of degradation processes. To further enhance reliability of the prediction, we integrate Adaptive Conformal Inference (ACI) with MSLR, enabling the estimation of statistically valid upper bounds for resistance degradation with high confidence. Extensive experiments demonstrate that MSLR outperforms state-of-the-art time series forecasting baselines on real-world PCB degradation datasets.
This work presents a supervised machine learning (ML) technique to suppress static and dynamic errors in time-interleaved (TI) successive-approximation-register (SAR) analog-to-digital converters (ADCs). Traditional methods rely on high-speed buffers and complex calibration algorithms to address reference ripple, gain mismatch, timing mismatch, and offset mismatch, increasing area/cost and design complexity. By contrast, the proposed ML-based approach uses a low-speed SAR ADC to digitally correct these errors, enhancing performance and lowering power consumption without requiring implicit knowledge of error sources or complex calibration procedures. The proposed ML calibration is demonstrated on a 2-channel time-interleaved ADC test-chip fabricated in 28nm CMOS and improves SNDR/SFDR by more than 21/38dB respectively.
This paper explores advanced voltage reference designs with extremely low power consumption, specifically under one microwatt. These designs are crucial for portable electronic systems that rely on minimal power. The paper categorizes these voltage references based on the types of devices used to generate temperature-proportional or complementary signals. It also provides key design examples to illustrate these concepts. Additionally, the paper enhances understanding by conducting a comparative analysis of performance metrics, including power consumption, temperature coefficient, physical size, and resistance to variations in the manufacturing process.
Matched circuit components are crucial for maximum efficiency in radio frequency (RF) systems, necessitating accurate load impedance monitoring. This paper proposes a method using reference point optimization with periodic structures for precise, low-overhead impedance measurements suitable for Built-in Self-Test (BIST). The novel technique uses a linear matching network and voltage detectors to sense load variations. A periodic structure measures voltages, and a multi-step algorithm selects optimal reference points to determine the load impedance.
Advancements in integrated circuit manufacturing technology and design complexity have been accompanied by challenges in efficiently ensuring product quality. Aggressive product usage scenarios in critical market segments, such as data centers and automotive, necessitate management of products throughout their lifetime ensuring graceful degradation and replacement. In this session, our first two presenters will discuss defect diagnosis methodologies to enhance product yield and manufacturing quality, while the final presenter will discuss methods to track and address in-field issues.
Adherence to the ISO 26262 standard requires periodic testing of embedded memories in automobiles, which must be completed within short time windows during normal vehicle operation. This testing must preserve memory contents post-test and integrate test logic seamlessly with system functionality, all while minimizing disruption to vehicle performance. This paper proposes a Memory Built-In Self-Test (MBIST) architecture that addresses these challenges by using a series of short test bursts. The architecture dynamically adjusts the length of each burst based on available memory idle time, ensuring efficient testing without interfering with critical system functions. Additionally, the architecture minimizes hardware overhead by reusing existing resources and introduces a direct access interface for tighter integration with system logic, further enhancing test efficiency and reducing latency.
The increasing complexity of semiconductor design, along with stringent performance, power, and time-to-market requirements, has outpaced the capabilities of traditional Electronic Design Automation (EDA) methodologies. Conventional design workflows rely on manual intervention for critical tasks such as hardware description, synthesis optimization, and verification, leading to inefficiencies and scalability limitations. Large Language Models (LLMs) present a transformative approach by automating key stages of the design pipeline, enabling intelligent synthesis tuning, test generation, and security analysis. This paper introduces ChipMind, an LLM-driven framework comprising specialized agents and modules for digital and analog chip design. ChipMind integrates AI-driven methodologies to enhance design efficiency, accelerate prototyping, and optimize key design trade-offs, thereby addressing fundamental challenges in modern semiconductor development.
Assertions are critical components used in hardware verification, ensuring robust functionality, fortifying design security, and providing essential verification features. Traditional hardware assertion methods are not automated, complicate security audits, and require effort, causing prolonged development cycles. Recent studies have highlighted the potential of commercial Large Language Models (LLMs) to generate security-focused assertions by leveraging textual data from design specifications. However, reliance on proprietary models like GPT-4 severely jeopardizes IP privacy and data confidentiality, undermining transparency and accountability in data handling practices. In this paper, we address secure hardware assertion generation by proposing a practical approach to significantly enhance the feasibility of open-source LLMs. Our proposed method, OpenAssert, involves fine-tuning existing models to be utilized locally at the user’s end without compromising confidentiality. Additionally, we employ Retrieval Augmentation Generation to refine these models, mitigating hallucinations and security-related errors. OpenAssert demonstrates improvements, achieving up to a 44% increase in rouge-1 score, a 49% improvement in cosine similarity, and a 43.4% reduction in word error rate for security-critical designs compared to open-source models.
Chip aging is a reliability concern for systems with long lifetimes. To detect defects that occur during the lifetime of a chip, in-field testing is applied when a system is turned on or off, as well as during idle periods. When in-field tests are designed for target faults, they target single faults, and may be invalidated when multiple faults are present. Although rare in general, this effect becomes more important when it involves defects that are likely to occur with aging. Addressing this situation in its most general form requires large numbers of multiple faults to be analyzed. This article suggests a solution based on a detailed analysis of situations where tests may be invalidated by multiple faults that are likely to occur with aging. The analysis results in small sets of faults and tests to detect them. The article demonstrates this approach by considering a situation involving double transition faults. Experimental results for benchmark circuits demonstrate the numbers of double transition faults that need to be considered and the numbers of tests for detecting them.
