Electrostatic dissipative polymers are used to control ESD in electronics and automotive industries, but rarely in applications that prevent ignitions of flammable substances. The risks of electrostatic hazards are generally reduced by connecting electrically conductive objects to earth. This technical paper shows advantages of dissipative polymers compared to conductive materials.
An effective approach to obtain optimal desired characteristics of HV dual-direction SCR ESD protection cell in HV power BCD process is presented. Based on experimental results the proposed dual direction system level ESD cell is realized in form of two independently optimized complementary sub-cells with dedicated positive P-DDSCR and negative N-DDSCR high current path.
ESD control items are generally characterized by direct current measurements at certain voltage levels. Discharge resistance may, however, have a remarkable voltage and frequency dependency. We have assessed conductive polymers by comparing the resistivities of the solid planar objects with the resistances of electrostatic discharges. Conductive polymers may have applicable characteristics of current attenuation for ESD control items.
In this invited paper, we provide an overview of the challenges and solutions to ensure Zero Defect (ZD) quality for the automotive semiconductor products from test viewpoint. We start with an overview of the defect classification and acceleration of latent defect, followed by review of recent developments of automotive semiconductor test. Next we present an overview of automotive production test flow and discuss the increased Electrical Over Stress (EOS) risk associated with Package-Level Burn-In (PLBI) and the recent work on reducing the risk using Wafer Level Stress for automotive semiconductors. Moreover, we will provide an in-depth review of the key advanced stress and test components including the enhanced High Voltage Stress Test (HVST) and enhanced Advanced Outlier Limits (AOL) screening and the enabling Design for ZD methodology, as well as their implication to EOS/ESD community.
An ESD analysis is carried out for bandwidth extension circuits composed of three inductor segments and integrated with distributed ESD protection. The tri-coil bandwidth extension circuit is proposed for wireline receivers. TLP and S-parameter measurements are used to benchmark the tri-coil’s performance against that of a more conventional T-coil.
System Level ESD and Fault protection co-design approach on high voltage tolerant transceivers is presented. Two-stage protection network is defined for the case of ±65V CANL output stage. Methodology incorporates dual-directional SCR overshoot at triggering, calculation of parameters for the fault protection snubber clamp and internal circuit pulsed SOA limits.
This paper presents a pioneering examination of using Machine Learning (ML) for applications to ESD data analysis. It involves demonstrating how post ESD stress IV curve data can lead to machine learning opportunities. The proposed technique can significantly reduce the iterations between product test and ESD design engineers and thus shortening time to market.
Transient latchup can result from system level stresses like the IEC61000-4-2 and cable discharge events. Latchup sensitive layouts should not be placed in the near vicinity of emitting junctions. This work determines the required safety distance for sensitive layouts from DC and TLP measurements at high temperature.
A hybrid finite difference model for an open base transistor with Kirk effect is presented. It solves the diffusion equation in a spice simulator. Impact ionization at the Base-Collector junction is included. The calculation results are compared with VF-TLP and TLP measurements and a very good agreement is achieved.
This paper describes a new method to assess the CDM-like risk for a device assembled on a printed circuit in board production. It shows that for a quantitative risk assessment for devices with a certain CDM robustness.
T-coil circuit is capable of mitigating the influence of parasitic capacitance in ESD protection circuits, but the mutual induced voltage reduces ESD robustness. In this study, HBM, CDM, TLP, and VF-TLP measurements were performed using a Test Element Group (TEG) developed with CMOS cutting-edge technology. The results show the peak current leading to destruction does not agree between CDM and VF-TLP, which was confirmed by the simulation. The T-coil circuit is a new case where TLP and ESD measurements do not correlate with each other.
Several physical insights into the multi-finger turn-on in deep junction GGNMOS devices and its implication on eventual failure current is presented with detailed experiments. The impact of junction depth to channel length ratio is found to be a key design factor in obtaining ESD robustness.
This technical paper provides a draft procedure for an alternative method of fast switching, AC ionizer, offset voltage measurement. It is more accurate than using a conventional charge plate monitor (CPM) which has a response speed limit of approximately 1-10 Hz. This was discussed in a previous study of CPM limitations presented at the 2019 ESD Symposium. This paper will also address other technical issues related to different voltage values from 6x6 inch and 1x1 inch plate assemblies connected to the same CPM instrument.
When performing the industry standard ANSI/ESDA/JEDEC JS-002 small module calibration, 15% difference in peak current was measured for the same setup with different oscilloscopes. This could cause a relatively large difference between the voltage factors used in the CDM setups and therefore a difference in CDM failure between different setups. In this paper, analysis of the frequency responses of the current sensor, signal chain, and oscilloscope measurement from a JS-002 CDM setup were studied. An oscilloscope frequency response characterization method was conducted, and the related frequency compensation method is discussed.
SoC can contain multiple silicon dies connected by die-to-die interfaces. These interfaces do not require additional on-chip ESD protection, but must survive through frontend and backend processes. In this study, die-to-die discharge current waveforms are analyzed using calculation methods for estimating ESD protection targets for the internal interfaces.
Heterogeneous bonding technologies are an attractive way to assemble high performance computing systems today. However, ESD risks of 2.5D/3D bonding are not fully understood. To help ESD control engineers and tool manufacturers, this paper describes the 2.5D/3D bonding processes and gives practical insights into the relevant ESD process assessment steps.
Parasitic bipolar devices are omnipresent in CMOS- or BCD-technologies and special consideration needs to be taken to avoid their unintentional triggering. This paper reviews the behavior of parasitic bipolars during ESD events. A novel characterization method to dynamically apply a base-emitter bias while pulsing collector vs. emitter is presented.
This work presents a compact model for N-Well ESD diodes, including the parasitic PNP. A schematic representation of the model is similar to the SPICE Gummel-Poon model, but the implementation differs. The proposed model uses a non-quasi-static description of the stored charge, which facilitates accurate simulation of the diode’s transient response to ESD. The very high-level injection which occurs during ESD is modeled in a manner suitable for the parasitic PNP with its relatively large base width.
Fast ESD events often cover the spectrum of the RF application circuit and imply a high impedance for passive ESD concepts. The resulting high voltage might destroy the RF-product. Very small ESD diodes improve the robustness of the chip against such fast transient events without significantly compromising the RF performance.
A simplified physics-based model for predicting the transient response and self-heating behavior of silicon-controlled rectifier (SCR) snapback-type transient voltage suppressors (TVS) is presented. Comparisons of the predicted quasi-static behavior and transient waveforms with measurements suggest that the proposed model accurately captures the most important characteristics of the device. Its simplified nature means it can be easily tuned using only data obtained from package-level measurements.
