Based on a recent pre-bond TSV probing technique, this paper proposes an iterative greedy procedure to sort the order of test sessions for reducing pre-bond TSV test time. We then combine that session sorting procedure with two existing methods to develop a 3-Step test time Optimization Simulator named “SOS3”. SOS3 consists of an ILP (integer linear programming) model for session generation, the greedy procedure for session sorting, and a TSV identification algorithm for early test termination. Experiments are done for various TSV networks and two observations are made. First, session sorting plays an important role within SOS3 as it helps to further reduce pre-bond test time expectation and thus reduces pre-bond TSV test cost. Second, SOS3 as a framework greatly speeds up the pre-bond TSV test.
Most processors employ hardware data prefetching to hide memory access latencies. However the prefetching requests from different threads on a multi-core processor can cause severe interference with prefetching and/or demand requests of others. The data prefetching can lead to significant performance degradation due to shared resource contention on shared memory multi-core systems. This paper proposes a thread-aware data prefetching mechanism based on low-overhead run-time information to tune prefetching modes and aggressiveness, mitigating the resource contention in the memory system. Our solution has two new components: 1) a filtering mechanism that informs the hardware about which prefetching requests can cause shared data invalidation and should be discarded, and 2) a self-tuning prefetcher that uses run-time feedback to adjust each thread's data prefetching mode and arguments. On a set of parallel benchmarks, our thread-aware data prefetching mechanisms improve the overall performance of 64-core system by 11% and reduce the energy-delay product by 13% over a multi-mode prefetch baseline system with a two level cache organization and a conventional MESI-based directory coherence protocol. We compare our approach to the feedback directed prefetching (FDP) technique and find that it provides better performance on multi-core systems, while reducing the energy delay product.
Stochastic computing (SC) is an approximate computing technique that represents data by probabilistic bit-streams called stochastic numbers (SNs). Arithmetic operations can be implemented at very low cost by means of SC. To achieve acceptable accuracy, interacting SNs must usually be statistically independent or uncorrelated. Correlation is poorly understood, however, and is a key problem in SC because of its impact on accuracy and the high cost of correlation-reducing logic. In this paper we analyze and quantify the role of correlation in stochastic circuit design. We use an algebraic framework based on probabilistic transfer matrices (PTMs) to analyze correlation-induced errors. We compare two systematic correlation-reducing methods, regeneration and isolation. Regeneration introduces new (pseudo) random sources to re-randomize SNs, while isolation uses delays (D flip-flops) to derive multiple independent SNs from a single random source. We present bounds on accuracy loss due to isolator insertion and compare its hardware cost to that of regeneration. We conclude that the isolation method can offer significant cost advantages in reducing correlation errors.
Extreme ultraviolet (EUV) lithography is one of the most promising next-generation lithography technologies, while chemical mechanical polishing (CMP) is the key planarization process for improving chip surface topography. The two techniques are highly related to layout pattern distribution and require different (even conflicting) distributions for EUV flare and CMP variation optimization to achieve better yields. Placement is a critical stage for controlling layout pattern distribution. In this paper, we propose the first work of simultaneous EUV flare-and CMP-aware placement to address the conflicting pattern distribution requirements with the two techniques. We present a sigmoid distribution model to reduce EUV flare effects and a metal-aware pin model to improve metal distribution. The two models are incorporated into a non-linear analytical optimization framework to achieve desired placement solutions. Experimental results show the effectiveness and efficiency of our proposed method.
Networks-on-Chips (NoCs) are experiencing escalating susceptibility to wear-out and reduced reliability, with the risk of becoming the key point of failure in an entire multicore chip. Aiming towards seamless NoC operation in the presence of faulty communication links, in this paper we propose Hermes, a highly-robust, distributed and lightweight fault-tolerant routing algorithm, whose performance degrades gracefully with increasing faulty link counts. Hermes is a deadlock-free hybrid routing algorithm, utilizing load-balancing routing on fault-free paths to sustain high-performance, while providing pre-reconfigured escape path selection in the vicinity of faults. Additionally, Hermes identifies non-communicating network partitions in scenarios where faulty links are topologically densely distributed. An extensive experimental evaluation, including utilizing traffic benchmarks gathered from full-system chip multi-processor simulations, shows that Hermes improves network throughput by up to 3× when compared against prior-art.
