Artificial intelligence (AI) is boosting the development of complex functionalities in the automotive domain, paving the way for autonomous decision-making capabilities of vehicles. However, integrating such complex functionalities at the system level is challenging due to the short time to market with limited development, verification, and validation periods. Moreover, automotive applications require compliance with strict safety regulations, which demands effective strategies to ensure timely development while allowing thorough dependability evaluations. This work addresses the system-level reliability of automotive applications by proposing a strategy named TIARA (Two-step IntegrAted Reliability Assessment) to assess the impact of hardware faults (modeled as soft errors) on AI-based perception tasks. Our strategy allows for the exploration and evaluation of algorithms, driving controllers, and critical operational scenarios, considering the effects of faults affecting the hardware up to the vehicle level. To tame the huge computational complexity, TIARA first exploits a static analysis to estimate the fault vulnerabilities and identifies the most critical code blocks. Then, the most critical application blocks (susceptible to faults from hardware) are targeted to evaluate the fault's impact on the vehicle dynamics and determine their effect at the system level, combining perception, control, and driving features. Our experimental results, obtained on a test case corresponding to a Lane Centering Assistance application based on the YoloP model and under different driving scenarios, show the feasibility and effectiveness of the proposed approach.
Nanosatellites have emerged as a viable alternative for space missions due to their adaptability, cost-effectiveness, and potential for data collection operations in Low Earth Orbit (LEO). However, high radiation exposure in LEO poses a significant risk, particularly to the reliability of embedded systems that are vulnerable to memory failures and critical data errors. This context creates the opportunity to develop solutions that ensure the integrity of data stored in memory, which is crucial for mission success and satellite reliability. To address these challenges, this paper presents a new, robust approach for error correction code (ECC) for memory systems used in space applications. The approach, namely NASCERR, is the result of a partnership between Brazilian public universities and the private sector, and aims to validate the ROBC (Robust On-Board Computer), an on-board fault-tolerant computer system for CubeSats. The approach was implemented in a SmartFusion2 M2S025 FPGA operating as an intermediary block (Man-in-the-Middle) between the processor and the SRAM memory system of the satellite. The approach is said to be self-tuning, by adjusting the error correction strategy transparently and on-the-fly, according to the type and frequency of errors detected in memory, in mission mode. Intensive simulation campaigns demonstrated the proposed approach presents high resilience, achieving 100% recovery rate in bit-flip occurrency, while guaranteeing high workload computational performance.
Silent Data Errors (SDEs), which corrupt or alter data without immediate detection, are an escalating concern for chip manufacturers and data centers. These errors can lead to serious consequences, especially when corrupted data is used in critical computing tasks. Their subtle and elusive nature makes SDEs particularly challenging to detect and address. This paper investigates manufacturing defects, specifically resistive opens, that have the potential to induce SDEs. We focus on defects that are undetectable by traditional Boolean-based testing methods and cause small delays in circuit behavior. The study also examines the challenges posed by FinFET technology, which, due to its reduced geometries, increased susceptibility, and the use of complex multi-fin and multi-finger structures, exacerbates the risk of SDEs. Furthermore, we explore how real-life operation conditions—such as IR-drop, crosstalk, and temperature variations—can contribute to the emergence of SDEs. Our findings identify certain resistive open defects as potential sources of SDEs and provide insights that could inform the development of enhanced manufacturing tests to mitigate these errors. This research offers a pathway to improving the robustness of chip designs and testing methodologies, ultimately reducing the impact of SDEs in critical systems.
Ensuring the reliability of complex Automotive System-on-Chips (SoCs) is critical. System-Level Test (SLT) is a vital yet relatively new approach that enhances traditional manufacturing tests by running real-world functional programs using specialized Automatic Test Equipment (ATE) and meticulously monitoring the results. A current industrial key challenge is gauging how well these SLT procedures exercise the SoC's resources. This work introduces a novel technique for multicore SoCs, that leverages execution trace analysis. We construct a comprehensive data flow graph by capturing different CPUs instruction traces during SLT. Dynamic analysis of this graph traces each data point to its destination. Our method accounts for inter-core synchronization, providing a holistic view of data flow. A custom metric quantifies overall data flow integrity. Tests on an STMicroelectronics automotive device demonstrate the method's efficiency and quantify significant gains in accuracy, time, and reduced human resources, promising more reliable automotive SoCs.
Physical Unclonable Functions (PUFs) and True Random Number Generators (TRNGs) have emerged as effective solutions for enhancing local security in digital devices, offering secure IC authentication and random cryptographic keys. Among the components used to implement these primitives, Ring Oscillators (ROs) play a pivotal role due to their simplicity, scalability, and ability to exploit process variability. However, the effectiveness of ROs is challenged by their susceptibility to various fault attacks that tamper with the working conditions. Among these attacks, ElectroMagnetic Fault Injection (EMFI) was underscored as a real threat to the RO frequency through harmonic locking. Therefore, this paper aims to explore the impact of voltage drop and temperature rise on the harmonic susceptibility of a RO under EMFI. Experiments involved deploying a grid of 4600 ROs across different FPGAs to highlight the increased intensity of harmonic errors due to the major effect of voltage fluctuations. Further EMFI campaigns with X-ray irradiation provided additional insights into the critical relationship between the RO frequency and its harmonic susceptibility to EMFI.
In a cyber-physical system (CPS), physical and digital components are deeply intertwined, making its design and verification a challenging process. To manage this complexity, hybrid automata are generally adopted to model CPS, allowing the representation of both its discrete and continuous behaviours, which are implemented in the digital and the physical parts. While some tools exist at the state of the art for either modelling or verifying hybrid automata, they present some drawbacks, specifically in terms of ease of use and lack of a unified tool that makes seamless the integration of design, simulation and verification steps. To fill in the gap, we present a new EDA tool for model-driven design and verification of hybrid automata. It does not require designers to learn domain-specific languages, as automatons are graphically modeled; furthermore, the tool integrates a simulation engine for analyzing the evolution of the automata and detecting design errors through the execution of checkers synthesized from Signal Temporal Logic (STL) assertions. The effectiveness of the proposed tool is demonstrated with a case study.
Nowadays, the Internet of Things (IoT) and edge computing paradigms drive innovation in several fields, including autonomous systems, environmental monitoring, smart farming, and surveillance. The wide adoption of IoT and edge computing through commercial-off-the-shelf (COTS) provides adequate computational resources under limited energy consumption and affordable prices, which allow the development of versatile, scalable, and adaptable systems for several domains. Both features (versatility and scalability) have brought attention to domains with strict dependability requirements. However, ensuring effective, reliable, fault-tolerant IoT systems is challenging and mostly neglected in some domains. This special session briefly overviews strategies for the reliable design of IoT and edge computing systems for environmental monitoring in smart farming and urban scenarios. Then, we analyze an emerging paradigm (Split computing) and its reliability features. Further-more, the session discusses and focuses on design challenges, learned lessons, reliability implications, and open questions.
With the growing presence of semiconductor devices in healthcare, automotive, and consumer electronics, Automatic Test Equipment (ATE) systems play an increasingly vital role in ensuring quality and reliability during validation. Despite their importance, ATE systems often operate in isolation from other manufacturing processes, limiting interoperability and integration potential. Consequently, fully incorporating ATE systems within the Industry 4.0 framework remains a largely unaddressed challenge. To bridge this gap, we propose adopting Open Platform Communications Unified Architecture (OPC UA), the industry de-facto standard communication protocol for machines, with an accompanying specification tailored to ATE systems. We developed and validated our information model on an advanced ATE system, demonstrating its practical application. The results showcase the successful integration of the ATE system into a fully-fledged Industrial Computer Engineering (ICE) laboratory demonstrator. This study validates the effectiveness of our model in a real-world scenario and highlights the significance of our integration approach within the context of Industry 4.0.
The concept of testability preserving or even testability improving circuit transformations has been studied intensively. It has been demonstrated for various fault models, that circuits can be optimized with respect to area and/or delay, while considering testability at the same time. Recently, Polynomial Formal Verification (PFV) has been introduced, where upper bounds on run time and space complexity of the algorithms - ensuring 100% correctness - are given. While the testability aspects were properties of the underlying circuits, here we propose a similar approach in the context of verification algorithms: verification preserving transformations and verification improving transformations. This is discussed for PFV, while the concept can be considered for formal verification techniques in general and also for simulation-based approaches.
Electronic devices intended for safety-critical industries, such as automotive, undergo extensive testing to ensure their reliability and compliance with safety standards. It is critical to constantly monitor, even in mission mode, that no failure due to wear and tear can compromise their reliability. Using self-testing circuitry such as Logic Built-In Self-Test (LBIST), it is possible to implement key-on and key-off tests to monitor the reliability status of the device also during its operational lifetime. This paper proposes a methodology based on LBIST data collection launched at key-on and key-off via CPU to improve the logic diagnosis of devices returned from the field. The proposed methodology exploits the reprogramming of pattern generation and signature compaction registers to retrieve information about all the failing and successful patterns instead of the sole generic fail information. As such, the proposal achieves better diagnostic effectiveness than other state-of-the-art methodologies. Experimental results show that the diagnosis has a significant increase in accuracy for an industrial automotive device manufactured by STMicroelectronics.
The main goal of this tutorial is to summarize some relationships and differences between reliability, safety and security and to emphasize the need for a more holistic design approach when hardening digital integrated systems having several requirements. Hardening for safety or reliability actually has advantages with respect to some security concerns, but usual proposals described in the literature do not meet all security needs. To achieve trustworthiness, additional constraints have to be taken into account during the design process to ensure an efficient protection against attacks, and still more important to avoid having counterproductive effects on the global security level. Some practical examples are discussed to illustrate the impact of security requirements on hardening at different steps of the design flow.
Simulation-based software fault injection is the most used method for fault injection whenever the verification of a system robustness or fault-tolerance capability is aimed. UVM-FI is a SystemC-based approach, proposed previously to enhance UVM libraries with fault-injection features. The current paper presents UVM-FIE, with key enhancements made to the previous version: The SystemC Code Converter to broaden the scope of supported variables, and the Random Fault Injector to automate fault injection into the RTL design. The improvements have been tested and validated with XINA, an Network-on-Chip (NoC) router design, demonstrating their ability to streamline fault injection in complex designs and promote system reliability through extensive fault testing.
The DUNE experiment studies neutrinos, fundamental particles that interact weakly with matter. This work describes the development of a subsystem for signal digitization on the DAPHNE card test bench, a critical component in the experiment's data acquisition. HDL designs were implemented on an FPGA, and pulses were generated using an ESP32 microcontroller, which were then converted to analog signals through its DAC. The evaluation was performed using the Analog Discovery 2 device. The results confirmed the correct implementation of the HDL designs, based on predefined data and difference equations. The difference equation-based model demonstrated greater dynamic processing capability, albeit with higher resource consumption, whereas the predefined data design proved more resource-efficient. This development enhances the evaluation of the DAPHNE board, increasing its reliability and adaptability within the context of the DUNE experiment.
The side-channel attack resistance of hardware implementations of cryptographic algorithms can vary significantly with operating parameters, such as operating voltage, clock frequency, temperature, etc. This study investigates the influence of temperature on the resilience of an ASIC implementation of the Montgomery ladder against SCA. We conducted a series of experiments to evaluate how varying temperature conditions impact the resistance of our ASIC to horizontal attacks. Our results reveal that in contrast to the state-of-the-art approach of increasing the operating temperature, operating under sub-zero temperatures can result in increased vulnerability to side-channel attacks compared to high temperature experiments. We present a detailed analysis of the thermal sensitivity of our ASIC, correlating specific temperature ranges with potential security degradation.
In current nanometer technologies, aging effects may appear after relatively short operating times, compared to the expected lifetime of circuits. Therefore, there is an increasing need to keep on analyzing circuit designs once they are in the field. This goal can be achieved by means of on-chip sensors. In this context, this paper presents a tiny on-chip sensor to monitor in-field aging of functional logic circuits. Experimental results based on extensive SPICE simulations demonstrate this approach is able to detect slight increase of circuit response time due to aging much earlier than a functional error is observed at the circuit output. This solution enables mission-mode monitoring of chip operation, which is a critical aspect of silicon lifecycle management framework. 64 aging sensors were integrated in a 6-stage 64-bit engine RISC-V processor and manufactured with the IHP 130 nm SiGe BiCMOS G2 technology. The area, power and delay side-effects resulting from the inclusion of the sensors into the processor were negligible. Moreover, in order to prevent the sensor from self-aging, it was coupled with a power gating circuitry to disconnect it from power-supply during idle times.
In safety critical systems, error-tolerant data transfer is essential, as noisy and stressful environments, parasitic elements, and high technology scaling can lead to data corruption and impact the system reliability and safety. This paper proposes a novel method that embeds error detecting information within the data blocks, ensuring zero data redundancy and avoiding any performance degradation. To achieve this, arithmetic coding is combined with approximate communication, making sure that the check information remains constant for the complete data transmission. The approximations are derived by an optimization process which minimizes the necessary deviations and exploits the remaining degrees of freedom to address the lifetime and the power dissipation of interconnect wires. Our experimental results demonstrate that, with minimum approximation, error-tolerant data transfer is ensured, and interconnect lifetime is enhanced.
The use of Resistive Random Access Memories (RRAMs) for implementing emerging applications depends not only on being able to properly test them after manufacturing but also on being able to guarantee their reliability during their lifetime. These novel non-volatile memories can be affected by manufacturing deviations, process variations and defects, as well as by time-dependent deviations, environmental and temporal variations. In more detail, RRAM's lifetime can be significantly reduced due to in-field degradation, since RRAM cell's endurance can be affected by different parameters, such as temperature and switching speed. In this context, this paper introduces the idea of modifying a Design-for-Testability (DfT) strategy proposed to perform manufacturing testing to also perform online testing aiming the identification of aged RRAM cells during lifetime. The proposed strategy requires the introduction of a DfT Aging Circuitry, based on a DfT Circuitry proposed to perform manufacturing testing only, for identifying faulty-free RRAM cells. The combined strategy was validated using a case study composed of a 4x4 words RRAM block implemented using 28nm TSMC technology library. Experimental results demonstrated the proposed strategy's detection capability. In more detail, these results show that the DfT Aging Circuitry is able to indicate not only when the RRAM cells do not reach the expected resistance values for each resistive state at time zero, but also when the RRAM cells are aged.
Convolutional Neural Networks (CNNs) have shown exceptional effectiveness in complex and data-intensive domains such as image and video processing, conversational systems, and healthcare. Moreover, sectors like High-Performance Computing and safety-critical applications, including automotive, aerospace, and autonomous robotics, impose stringent requirements on energy efficiency, performance, and robustness. However, modern semiconductor technologies are increasingly vulnerable to faults, which can degrade CNN performance and potentially result in catastrophic failures. This work explores the impact of regularization techniques (dropout layer) in enhancing the inference robustness of CNN models against soft errors. We analyzed soft error impacts on five widely adopted CNN architectures, each trained with ten different dropout rates. Our experimental results reveal that optimizing the dropout rate during training can improve the in-field robustness of CNN models by up to 12% compared to baseline configurations under soft error conditions. Additionally, fine-tuning this architectural parameter can lead to accuracy improvements of up to 10%.
In recent years, research and technology advancements have driven exponential growth in the adoption of Artificial Intelligence (AI)-based systems, even in safety-critical contexts such as autonomous driving and healthcare applications. The joint effort of academia and industry has yielded techniques and standards with the objective of ensuring the safe operation of AI-based technology. In the specific context of Convolutional Neural Networks (CNNs) running on GPUs, Image Test Libraries (ITLs) have been proposed as an effective method for performing on-line functional testing of GPU multipliers. This is achieved by launching the inference of a set of test images containing a set of ATPG-generated functional test patterns. However, while the demand for computational power for DNN models is constantly increasing, another branch of Machine Learning (ML) research, namely TinyML, focuses on minimizing the computational requirements of DNN models in order to bring AI capabilities to edge devices, whose constraints on power usage, memory space and processing power do not allow for the deployment of conventional DNN models. This research work aims to adapt the ITL technique to CNNs running on ultra-low-power edge hardware, while also overcoming some limitations of GPU ITLs. Experimental results demonstrate that a single test image generated using the proposed method is capable of detecting 96.01% of stuck-at faults occurring in the 32-bit integer multiplier of a RISC-V-based ultra-low-power System-on-Chip executing a quantized CNN.
The RISC-V architecture has become increasingly popular due to its open-source nature and flexibility, making it susceptible to various security attacks, such as Stack Buffer Overflow (SBO) attacks. It is crucial to effectively detect these attacks to ensure the security of RISC-V systems. This study explores Hardware-Supported Malware Detection (HMD) techniques for identifying these security threats. Using the CV32e40p RISC-V platform, we conducted simulations to assess the effectiveness of anomaly-based HMD methods in detecting SBO attacks by analyzing hardware microarchitectural events. The findings demonstrate the potential of these approaches but also reveal significant challenges in detection performance. These elements are essential for advancing the security capabilities of HMD systems in RISC-V environments.
