Partition of monolithic 2D (M2D) chip and heterogeneous integration of resultant chiplets are inevitable in the near future due to rising cost of transistor and complexity of process. 3D stacking is required to maintain tight cross-IP communication and fit into the limited footprint over Printed Circuit Board (PCB). We discuss criteria of choice for the 3DIC technology flavor and logic chiplet scaling knobs in terms of optimized key performance indicators (KPI) at system level.

Standard cell track height scaling provides us with sufficient area scaling at the standard cell library level. The efficiency of this technique and the complexities involved with this scaling method have been discussed in detail [1,2]. However, the area benefits of standard cell track height scaling diminish when we consider the complexities of incorporating on-chip power grid into the DTCO exploration loop. We have previously outlined several layout techniques to improve the utilization density of this scaling technology [2,4]. However, the proposed techniques only minimize the impact of the power grid on the design. In this work, we discuss the need to combine 3D – μTSV technology and logic technology to decouple the power grid from the design budget. The proposed technique delivers power from the backside of a thinned device wafer using the process steps depicted in Figure 4. Our analysis demonstrates significant area savings and IR-drop reduction. We use SPICE simulations to extract grid resistances as part of our technology targeting process, based upon a high-level on-chip PDN model. We also verify our findings using a commercially available EDA toolchain.

In this article, a power delivery network (PDN) modeling framework for backside-PDN configurations is presented. A backside-PDN configuration contains dense microthrough silicon vias ( $\mu $ TSVs) and power/ground metal stack on the backside of the die. This approach separates the PDN from a conventional signaling network of the back-end-of-the-line (BEOL) and improves power integrity and core utilization. We benchmark this technology with conventional front-side BEOL PDN configurations. Owing to the lower resistivity compared with Cu metal lines for advanced technology nodes, we use ruthenium (Ru)-based buried power rail for PDN modeling. Our analysis shows that the steady-state IR-drop reduces by more than $4\times $ in the backside-PDN configuration, and a simultaneous switching noise analysis shows a significant reduction in transient droops. The framework results are validated with a place-and-route (PR)-based physical implementation flow. We quantify the area improvement in the actual flow and observe 25-30 improvement in the backside-PDN configuration. From a PDN modeling framework, the PDN results follow a trend similar to the ones obtained from the block-level PR of the given configurations. Moreover, we investigate the impacts of package-to-die interconnect pitch, metal-insulator-metal cap density, and input pulse on the PDN performance. In addition, we perform thermal modeling to analyze the thermal implications of the backside-PDN configuration. From a thermal modeling perspective, there is negligible influence from a dielectric bonding layer in the backside-PDN configuration.

To ensure continuity in technology scaling, system level technology boosters will need to be introduced to complement Design-Technology Co-Optimization. We illustrate this evolution with the introduction of buried power rails and backside power delivery. These can provide 20% and 30% area scaling benefit respectively. Backside power delivery further improves IR drop providing up to 15% performance enhancement enabling PPAC scaling at system level.

This letter proposes for the first time buried powered static random-access memory (SRAM) to achieve enhanced write margin and performance in advanced CMOS technology nodes. The buried power rail (BPR) for SRAM is silicon verified. The BPR helps to lower the bitline and wordline resistance by relaxing metal width in SRAM circuits and thereby enhances the write margin and performance. The proposed SRAM provides up to 340 mV and 30.6% improvement in write margin and read speed, respectively, as compared to its conventional counterpart without incurring any area penalty in a hardware influenced 3 nm CMOS technology.

High-aspect-ratio (HAR) Ru power rails, buried in front-end-of-line (FEOL) oxide, can potentially replace conventional middle-end-of-line (MOL) Cu power rails. The HAR feature can boost performance by reducing resistance and voltage drop along the power line. The buried nature, helps to minimize standard cell height by freeing up routing resources at MOL, enabling overall area scaling. This paper demonstrates, Ru lines of aspect ratio up to 7, at a CD of 18 nm. Line resistance at these dimensions, measures at 60 Ω/µm, with the minimum electrical resistivity of 8.8 µΩcm, as extracted from the temperature-controlled-resistance (TCR) measurements. HAR Ru lines are also found to withstand very high FEOL thermal budgets, such as 1000 °C activation anneal for 1.5 s. The combination of all these factors, make HAR Ru buried power rail, a promising scaling booster for next generation technology nodes.

Standard cell track height scaling has been identified as an option to provide significant area savings. A direct consequence of track height reduction is that the width of the power rails needs to be reduced to accommodate patterning constraints as well as leave sufficient tracks for routing. Narrower power rails are highly resistive, reducing the headroom near an operating cell due to IR drop, which is not acceptable. For example, a 20% performance loss is observed due to a 10% supply voltage drop. To worsen the situation of IR drop, a slowdown in CPP scaling and newer metallization options are making the power rail highly sensitive and its design choice is a widely debated topic in the industry. Therefore, we propose an approach to define the power rail specifications and some feasible technology solutions to solve the power grid bottleneck.

Standard-cell design, technology choices, and place and route (P&R) efficiency are deeply interrelated in CMOS technology nodes below 10 nm, where lower number of tracks cells and higher pin densities pose increasingly challenging problems to the router in terms of congestion and pin accessibility. To evaluate and downselect the best solutions, a holistic design-technology co-optimization approach leveraging state-of-the-art P&R tools is thus necessary. We adopt such an approach using the imec N7 technology platform, with contacted poly pitch of 42 nm and tightest metal pitch of 32 nm, by comparing post P&R area of an IP block for different standard cell configurations, technology options, and cell height. Keeping the technology node and the set of ground rules unchanged, we demonstrate that a careful combination of these solutions can enable area gains of up to 50%, comparable with the area benefits of migrating to another node. We further demonstrate that these area benefits can be achieved at isoperformance with >20% reduced power. As at the end of the CMOS roadmap, conventional scaling enacted through pitch reduction is made more and more challenging by constraints imposed by lithography limits, material resistivity, manufacturability, and ultimately wafer cost, the approach shown herein offers a valid, attractive, and low-cost alternative. (C) 2018 Society of Photo-Optical Instrumentation Engineers (SPIE)

In this paper, standard cell design for iN7 CMOS platform technology targeting the tightest contacted poly pitch (CPP) of 42 nm and a metal pitch of 32 nm in the FinFET technology is presented. Three standard cell architectures for iN7, a 7.5-Track library, 6.5-Track library, and 6-Track library have been designed. Scaling boosters are introduced for the libraries progressively: first an extra MOL layer to enable an efficient layout of the three libraries starting with 7.5-Track library; second, fully self aligned gate contact is introduced for 6.5 and 6-Track library and third, 6-Track cell design includes a buried rail track for supply. The 6-Track cells are on average 5% and 45% smaller than the 6.5 and 7.5-Track cells, respectively.

Standard-cell design and characterization are presented for 7-nm CMOS platform technology targeting low-power and high-performance applications with the tightest contacted poly pitch of 42 nm and a metallization pitch of 32 nm in the FinFET technology. Two standard-cell architectures for 7 nm, a 9-track library and a 7.5-track library have been designed, introducing an extra middle-of-line layer to enable an efficient layout of the 7.5-track cells. The 7.5-track cells are on average smaller than the 9-track cells. With the strict design constraints imposed by self-aligned quadruple patterning and self-aligned double patterning, careful design and technology co-optimization is performed. (C) 2016 Society of Photo-Optical Instrumentation Engineers (SPIE)

At 7nm and beyond, designers need to support scaling by identifying the most optimal patterning schemes for their designs. Moreover, designers can actively help by exploring scaling options that do not necessarily require aggressive pitch scaling. In this paper we will illustrate how MOL scheme and patterning can be optimized to achieve a dense SRAM cell; how optimizing device performance can lead to smaller standard cells; how the metal interconnect stack needs to be adjusted for unidirectional metals and how a vertical transistor can shift design paradigms. This paper demonstrates that scaling has become a joint design-technology co-optimization effort between process technology and design specialists, that expands beyond just patterning enabled dimensional scaling.

This work addresses the difficulties in creating a manufacturable M2 layer based on an SADP process for N10/N7 and proposes a couple of solutions. For the N10 design, we opted for a line staggering approach in which each line-end ends on a contact. We highlight the challenges to obtain a reasonable process window, both in simulation as on based on exposures on wafer. The main challenges come from a very complex keep mask, consisting of complicated 2D structures which are very challenging for 193i litho. Therefore, we propose a solution in which we perform a traditional LELE process on top of a mandrel layer. Towards N7 we show that a line staggering approach starts to break down and design needs to allow better process window for lithography by having metal lines ending in an aligned fashion. has many challenges and we propose to switch to a line cut approach. A more lithography friendly approach is needed for design where the lines end at aligned points so that the process window can be enhanced.

While waiting for EUV lithography to become ready for adoption, we need to create designs compatible with both EUV single exposures as well as with 193i multiple splits strategy for technology nodes 7nm and below needed to keep the scaling trend intact. However, the standard approach of designing standard cells in two-dimensional directions is no more valid owing to insufficient resolution of 193-i scanner. Therefore, we propose a standard cell design methodology, which exploits purely one-dimensional interconnect.

The density requirement expected for the 10nm node continues to increase the pressure on patterning. With the frontend of line adopting a regular layout (mostly unidirectional), most of the complexity needed for a functional chip ends up in the interconnect layer and Metal1. Assuming that Extreme Ultra Violet Lithography (EUVL) will not be ready for the early stage of 10nm production but only for high volume manufacturing, we have studied how ArF immersion lithography can be extended for Metal1 to sustain the development of the technology as well as the early production phase, while at the same time remaining compatible with an EUVL single patterning solution. We show how close interaction between design, process and computational lithography leads to a Metal1 triple patterning solution using Negative Tone Development (NTD), and how the same design solution can be supported by EUVL single patterning. Particular attention will be paid to line end printability performance, both tip to tip and tip to line, as we believe it is a key parameter to define the best compromise between lithography performance and design density.

Design-Technology co-optimization becomes a key knob to enable CMOS scaling. In this work we evaluate the technology options including lithography options as well as device options that are considered to enable N10 scaling by exploring their impact on representative designs such as standard cells, SRAM and analog contexts. This paper illustrates that the design angle needs to be considered early in the development of a technology node. This design assessment and decisions start from lithography constraints and options to power/performance, area and cost, all of which create the Design-Technology Co-Optimization space.

This paper proposes TEASE (Technology Exploration and Analysis for SoC-level Evaluation), a framework to systematically analyze and evaluate system design in finFET-based technology node. The proposed framework combines both lithography and electrical constraints of a particular technology node to optimize the standard cell library performance. Growing complexity of logic design at nodes below 20nm causes to adopt a design style that can embrace the simplicity required to enable manufacturing, along with a process technology that can be finely tuned to the desired performance constraints. Additionally, the introduction of finFET based devices poses a new challenge for the designers to come up with an efficient standard cell template. The proposed framework can be used to detect the technology constraints that act as the bottleneck for the enablement of design at these advanced nodes. Results presented in this paper show by optimizing these bottlenecks we can improve the performance of a standard cell library significantly. Furthermore, adapting to such an analysis framework at an early stage of technology development helps to take the design constraints into the decision loop for realization of technology research into real products.

Field-programmable gate arrays (FPGA) are drawing increasing interest because of its performance, power consumption and configurability. They execute wide range of parallelizable algorithms which changes in accordance to variations in wireless channel statistics are utilized in smart antenna array embedded systems. In this article, we've described the FPGA implementation of a QRD processor that enables the run-time definition of the input matrix dimensions. The design employs a mixture of CORDIC-based processing (array boundary cell) and MAC based (array internal cell) arithmetic that is well matched to the computational resources of an FPGA like the Xilinx Virtex-2 Pro. We have made a projection of resource estimation for the processor when implemented as a whole array and as an embedded system with a micro processor and reduced number of internal and boundary cells.