We report on aggressively scaled replacement metal gate, high-k last (RMG-HKL) planar and multi-gate fin field-effect transistor (FinFET) devices, systematically investigating the impact of post high-k deposition thermal (PDA) and plasma (SF6) treatments on device characteristics, and providing a deeper insight into underlying degradation mechanisms. We demonstrate that: 1) substantially reduced gate leakage (J G) and noise can be obtained for both type of devices with PDA and F incorporation in the gate stack by SF6, without equivalent oxide thickness (EOT) penalty; 2) SF6 enables improved mobility and reduced interface trapped charge density (N it) down to narrower fin devices [fin width (W Fin) ≥ 5 nm], mitigating the impact of fin patterning and fin sidewall crystal orientations, while allowing a simplified dual-effective work function (EWF) CMOS scheme suitable for both device architectures; 3) PDA yields smaller, in absolute values, PMOS threshold voltage |V T|, and substantially improved reliability behavior due to reduction of bulk defects.

2013 International Conference on Solid State Devices and Materials,Thermal and Plasma Treatments for Improved (Sub-)1nm EOT Planar and FinFET-based RMG High-k Last Devices and Enabling a Simplified Scalable CMOS Integration Scheme

The early detection of Cu sub-surface voids in nano-interconnects has become a main challenge with the reduction of the critical dimensions of the interconnects. A new methodology for full wafer Cu void inspection with high sensitivity and high speed has been developed using a Multi-Purpose SEM (MP-SEM) using high accelerating voltage, high resolution and multi BSE detectors. This inspection methodology has been used to evaluate the Cu metallization quality in nanointerconnects. The effectiveness of this inspection methodology was proven through the evidence of relations between Cu void density, trench widths, pattern density, and surrounding dummy structures.

Thin (<4 nm) Physical Vapor Deposited (PVD) Ru-10 at.% Ta films were evaluated as diffusion barriers and seed enhancement layers for Cu metallization in sub 25 nm trenches. The ratio of Ru/Ta on blanket wafers could be influenced by changing the process conditions. However, a difference in Ru/Ta ratio did not influence the thermal stability of the layers during High Temperature X-ray Diffraction (HT-XRD) measurements as all RuTa films exhibited good thermal properties since no Cu-silicide formation was observed for temperatures below 500 °C. The RuTa films also passed an 85 °C/85% relative humidity (RH) test of one week of storage in order to test the H2O barrier integrity of the films. Furthermore no difference was found when testing the O2 barrier integrity during 300 s anneals at various temperatures between 250 °C and 500 °C. Good Cu fill of 20 nm trenches (AR 4:1) patterned in oxide was achieved when combining the RuTa films with PVD Cu seed layers with thicknesses ranging from 7 to 20 nm and Cu plating. When compared to a Ta(N)/Ta barrier, relatively high electrical yields (60–80%) were obtained for structures with CDs <30 nm when combining RuTa films with PVD Cu seed layers as thin as 7 nm (on field), hence evidencing the seed enhancement ability of these layers.

This paper presents for the first time a low-complexity high performance CMOS HK/MG process on planar bulk Si using a single dielectric / single metal gate stack and making use of dual-channel integration. Through the optimization of the Si45Ge55/Si cap deposition and the workfunction metal, high performance devices with balanced Vt,sat (+0.12V, -0.16V) at scaled Tinv~1nm and gate length Lg~30nm are reported, leading to 17ps ring oscillators at 1μW/stage at Vdd=0.7V. Compatibility with gate last processing is also demonstrated.

Scaling air-gap interconnects to 70nm pitch is demonstrated for the first time by combining air-gap technology (SiO2 etch-back and non-conformal CVD) and the double patterning approach. A capacitance reduction of 45% was measured on the air-gaps compared to the SiO2 reference. The reliability performance of the air-gaps was then evaluated and it was found that the structures exceeded 10years lifetime at 2MV/cm, almost matching the performance of SiO2 interconnects. Air-gaps could therefore make a promising low-RC solution for future technology nodes.

We report high yield sub-0.1 mu m(2) SRAM cells using high-k/metal gate finfet devices. Key features are (1) novel fin patterning strategy, (2) double gate patterning (3) new SRAM cell layout and (4) EUV lithography and robust etch/fill/CMP for contact/metal1. 0.099 mu m(2) finfet 6T-SRAM cells show good yield. And smaller cells (0.089 mu m(2)) are functional. Further yield improvement is possible by junction optimization using extension less junction approach and further cell layout optimization.

Aurora® LK HM (k=3.2) material has been successfully integrated into 30 nm half pitch structures. This material outperforms Aurora® LK (k=3.0) in terms of breakdown field strength and mechanical properties. Scaling of the physical vapor deposition (PVD) based barrier/seed process and adjusting of the barrier chemical mechanical polishing (CMP) overpolish condition were yield enabling factors. No degradation of the breakdown field upon reducing half pitch is observed down to 30 nm for line lengths up to at least 1 mm. The median time-dependent dielectric breakdown (TDDB) lifetime, as evaluated on a 1 mm 35 nm half pitch parallel line structure, exceeds 10 years at an electrical field of 2.6 MV/cm.

Carbon nanotubes (CNT) are considered a promising material for interconnects for future generation microchips. The integration of vertical CNT in a processing environment is evaluated in this work. Hypothetical CNT-based interconnects are compared with existing technologies at different hierarchy levels including the limitations of present deposition methods for copper and tungsten. For practical benchmarking, CNT bundles were selectively grown into contact holes using PVD and ECD cobalt or nickel catalysts. A polishing step was used to control the CNT length after embedding the CNT into an oxide matrix. A CNT metal decoration method based on electrodeposition is presented which can be used to assess the yield of electrically conductive CNT as well as to form top-contacts for electrical characterization. Finally, the importance of having suitable and robust structures for evaluating the integration process is highlighted after the electrical characterization of CNT in a nanoprober station.

As copper interconnect structures are shrinking with each technology node novel metals other than PVD Ta(N)/Ta are being introduced as barrier materials. These materials act as seed enhancement layers and enable the Cu filling of the narrowest structures. However, the integration of such metals into the manufacturing of sub-35 nm wide Cu lines produces several challenges which need to be addressed. One of these challenges is the compatibility of the interconnect metals with the copper Chemical Mechanical Polishing (CMP) step. In particular, corrosion issues and Cu defectivity in the trenches need to be controlled. An evaluation of the compatibility of the CMP slurries with the new incorporated materials therefore becomes extremely important. Our work shows that by optimizing the CMP process and selecting compatible slurries, novel metals such as CVD Co (combined with a Ta(N) barrier) are promising candidates for the metallization of sub-35 nm lines.

We investigated a wafer level Cu/low-k thickness measurement technique and compared it to the electrical and surface profiling techniques. With this optical technique, we can achieve a comprehensive within-die and within-wafer Cu/low-k thickness monitoring which allows for a more accurate Cu CMP process control in advance Cu/low-k damascene structures.

We demonstrate electrically functional 0.099 mu m(2) 6T-SRAM cells using full-field EUV lithography for contact and M1 levels. This enables formation of dense arrays without requiring any OPC/RET, while exhibiting substantial process latitudes & potential lower cost of ownership (single-patterning). Key enablers include: 1) high-k/metal gate FinFETs with L-g similar to 40nm, 12-17nm wide Fins, and cell beta ratio similar to 1.3; 2) option for using an extension-less approach, advantageous for reducing complexity with 2 less I/I photos, and for enabling a better quality, defect-free growth of Si-epitaxial raised S/D; 3) use of double thin-spacers and ultra-thin silicide; 4) optimized W metallization for filling high aspect-ratio, >= 30nm-wide contacts. SRAM cell with SNM>10%V-DD down to 0.4V, and healthy electrical characteristics for the cell transistors [SS similar to 80mV/dec, DIBL similar to 50-80mV/V, and vertical bar V-Tlin vertical bar <= 0.2V (PMOS), V-Tlin similar to 0.36V (NMOS)] are reported.

The dielectric reliability of Aurora® LK (k = 3.0) material has been evaluated on a 50 nm half pitch test structure. These were fabricated using a double patterning scheme and TiN metal hard mask. The introduction of a suitable post-etch residue removal step and close-coupled processing between Cu electroplating and chemical mechanical polishing were found to be key for achieving high yield. Median time-dependent dielectric lifetime of 10 years is reached at an electrical field of 1.4 MV/cm, comparable to earlier reported results with SiO2 as dielectric. The reliability performance is found to be significantly layout dependent with corners being weak points due to local field enhancement.

Narrow trenches with Critical Dimensions down to 17 nm were patterned in oxide using a sacrificial FIN approach and used to evaluate the scalability of TaN/Ta, RuTa, TaN + Co and MnOx metallization schemes. So far, the RuTa metallization scheme has proved to be the most promising candidate to achieve a successful metallization of 25 nm interconnects, providing high electrical yields and a good compatibility with the slurries used during CMP.

In this paper we report on Cu plating of through-Silicon-vias (TSV-s) with a thin Ta film on the field. The thin Ta film is sputtered on top of the Ta barrier/Cu seed, and inhibits Cu plating outside the TSV-s. We show that the use of this Ta-cap and in situ electrochemical monitoring techniques leads to significant savings in plating and polishing time, and thus savings in manufacturing costs of 3D-stacked integrated circuits (3D-SIC).

Abstract AuroraLK HM (k=3.2) material has been successfully integrated in 30nm 1⁄2 pitch structures. This material outperforms AuroraLK (k=3.0) in terms of breakdown field strength and mechanical properties. Scaling of PVD based barrier/seed process and fine-tuning of the barrier CMP overpolish condition were yield enabling. No degradation of the breakdown field is observed at 30nm 1⁄2 pitch for line lengths up to at least 1mm. The median TDDB lifetime, evaluated on a 70nm pitch structure, exceeds 10 years at an electrical field of 0.7MV/cm.