A moving grid algorithm is presented for simulation of 3D oxidation processes. The algorithm combines local displacement of mesh points according to material velocity and local mesh cleanup. Several examples are shown that demonstrate the capabolity to simulate both the growth of thin layers of oxide during polysilicon gate reoxidation, as well at stress dependent growth of 3D locos oxides.

Shrinking feature sizes, novel device designs as well as stress engineering increase the need for three- dimensional process and device simulations. We present several application examples for full 3D process and device simulations using Sentaurus TCAD, including a 3D NMOSFET with shallow trench isolations (STI), a PMOSFET device with SiGe pockets for stress engineering (similar to the structure presented in Ref. [1]) and a Omega-FinFET (similar to structures presented in Refs. [2,3]). TCAD simulations of the full process flow as well as of the electrical device characteristics are performed. We also show examples of 3D oxidation simulations with Sentaurus Process.

This paper discusses different aspects of modeling the impact of stress on silicon processes and devices. The models account for the stresses due to the thermal mismatch during the temperature ramps, volume expansion and shrinkage, lattice mismatch stress due to the material composition and impurities in the lattice. It is important to simulate the evolution of the stresses coming from different sources in order to determine total stress distribution during the process flow. The peak stresses generated during the process steps might create extended defects, while the residual stresses at the end of the process flow determine the electrical performance of the device.

Analysis of the current trends in the semiconductor industry suggests that a number of novel simulation methods need to be explored. Several interdisciplinary simulation tools ranging from lithography and optical proximity correction to 3D continuum and atomistic process models have been integrated into a single simulation flow. Application of this tool suite to a typical 100nm nchannel MOSFET reveals a number of 3D effects that considerably impact its performance.

It is a known fact that melted glass, such as SiO/sub 2/, shows viscoelastic behavior. But in the range of processing temperatures the mechanical properties of SiO/sub 2/ vary strongly. While below 800/spl deg/C the material behaves like an elastic solid, at temperatures above 1000/spl deg/C it shows nearly pure viscous properties. In this paper, the governing equation, the so-called constitutive equation, describing viscoelastic behavior, and its discretization are presented. The oxide viscosity depends on the local amount of shear stresses which leads to inhomogeneous material behavior and a nonlinear theory. This new mechanical model was implemented into the process simulator DIOS-ISE. Some obtained simulation results are shown and discussed.

Atomistic computer simulations based on the binary collision approximation (BCA) are very well suited to predict the dependence of as-implanted dopant profiles on implant parameters like energy, dose and direction of incidence as well as on the arrangement of oxide, poly-Si and other materials on the single-crystalline Si substrate. In particular channeling effects, the enhanced dechanneling due to accumulation of radiation defects during ion bombardment and due to pre-existing ion-beam-induced defects can be simulated in a reasonable manner. The BCA code Crystal-TRIM was successfully integrated into 1D and 2D process simulators for the Si technology. The application of the trajectory splitting algorithm and the lateral duplication method ensures a high computational efficiency.

In the simulation of semiconductor processes and devices it may be necessary to generate surface parallel meshes. One important example occurs in MOS transistors where the electrons flow along the silicon surface underneath a gate. It is desired beneficial in terms of accuracy to have rather long mesh edges parallel and rather small edges orthogonal to those currents. For most of the devices quadtree techniques have been used with big success (Garreton G. A hybrid approach to 2D and 3D mesh generation for semiconductor device simulation. PhD Thesis, Integrated Systems Laboratory, ETH Zurich, 1999. Garreton G, Villablanca L, Strecker N, Fichtner W. Unified grid generation and adaptation for device simulation. Proceedings of SISDEP'95, Erlangen, Germany, 6-8 September 1995; 6:468-471.) If the interface is not axis aligned, however, a quadtree-based approach does not generate meshes of this quality, resulting in a larger numerical error or in convergence problems during equation solution.We present here a modified advancing front grid generator that inserts surface parallel mesh lines; the interior of the region is filled with layers of nearly rectangular quadrilaterals, and not triangles as in conventional advancing front generators (see George FL, Sveno E. The advancing front mesh generation method revisited. international Journal for Numerical Methods in Engineering 1994; 37:3605-3619 and Schoberl. Computing and Visualization in Science 1997; 1:41-52). Here we follow references of Johnston BP, Sullivan JM. Fully automatic two dimensional mesh generation using normal offsetting. International Journal for Numerical Methods in Engineering 1992; 33:425-442; Blacker TD, Stephenson MB. Paving: a new approach to automated quadrilateral mesh generation. international Journal for Numerical Methods in Engineering 1991; 32:811; Rees M. Combining quadrilateral and triangular meshing using the advancing front approach. Proceedings of the 6th International Meshing Roundtable 1997; 337-348; White DR, Rinney P. Redisign of the paving algorithm: robustness enhancements through element by element meshing. Proceedings of the 6th International Meshing Roundtable 1997; 323-335, but we use a different point location scheme, in the sense that the opposite edge of the quadrilateral is kept parallel if possible. At each layer the marching distance is increased by a coarsening factor; refinement is therefore controlled by the initial marching distance and the coarsening factor. A maximum edge length is guaranteed.The generation of offsetting layers stops when the front intersects itself. The remaining polygon is triangulated. As a final step the mesh is converted to a Delaunay conforming mesh by swapping edges and inserting points.The implementation in two dimensions has been tested successfully using realistic examples from device simulations. Copyright (C) 2000 John Wiley & Sons, Ltd.

We present the latest results of our research regarding meshes suitable for both process and device simulation. Two major results are discussed in this paper: a consistent multi-dimensional mesh quality definition and a new hybrid multi-dimensional mesh generation approach. The consistent definition achieved is based on the conditions imposed by the Box integration method applied for both semiconductor process and device equations. The hybrid approach developed reaches a consistent mesh quality in all dimensions and it overcomes the severe limitations of our former mesh generators. Finally, it has been experimentally demonstrated that both the unified conditions and the hybrid approach are suitable for stable discretization schemes for device simulations based on the Box method.

The successful integration of the binary collision code Crystal-TRIM into the 2D-process simulator DIOS as an optional module is reported. The new module is applied to the simulation of the formation of LDD-like structures. The use of a trajectory split method in combination with a mechanism for the lateral duplication of ion trajectories enables the simulation of the implantation step in extended targets with good depth and lateral resolution within reasonable computation times.

We propose to use a fixed damage factor combined with an effective dose to generate an initial interstitial silicon concentration profile at a given B ion implantation conditions and demonstrate that this methodology can readily explain transient enhanced diffusion (TED) in almost all relevant cases of practical VLSI processing. We also developed a B cluster reaction model which enables us to tune time evolution of active B profiles in a flexible way.

In this paper, we study the effect of high-dose BF/sub 2/ implantation/annealing sequences on the redistribution of dopant atoms already present in silicon crystal. Transient diffusion and activation effects are investigated using numerical simulation and experimental data obtained from silicon samples containing a buried layer of boron.

Analyzing experimental boron transient diffusion profiles in Si MOSFETs over a wide temperature range with the process simulator TESIM, we evaluated the related transient diffusion time t/sub E/, enhanced diffusivity D/sub enh/, and maximum transient diffusion concentration C/sub enh/. Our extracted values contradict previously reported values, but it is due to the fact that the former works neglected the ramp-up period. We show that considering the ramp-up period is indispensable for the analysis of transient diffusion. We also developed analytical models for t/sub E/, D/sub enh/, and C/sub enh/, and clarified their dependence on physical parameters implemented in TESIM.

The effect of BF2 implants on the transient and steady-state diffusion and activation behavior of boron has been investigated experimentally and analyzed using numerical simulation. The observation of retarded diffusion of boron in the BF2 case can be modeled by attributing interstitial trapping properties to fluorine. Transient activation could be accounted for using a single set of parameters in a nonequilibrium cluster model. Experimental results confirm that transient diffusion effects are suppressed in the case of BF2. A comparison of 30keV and 135 keV BF2 implantation/annealing sequences indicates that a marked influence of fluorine on boron seems to be present only for implants with higher energies.

This article gives an overview of our current state of the art in generating 3D geometry and doping representations for complex semiconductor devices. Focusing on the multidimensional aspects, we describe how-starting from the mask layout and the standard process representation (SPR)-the 3D device geometry and doping distribution is built by assembling simulations of different dimensionality.

This paper describes the design and development of a dimension-independent grid generator suitable for device simulation. The purpose of this work is to describe a modular, flexible and dimension-independent approach for the generation of grids with complex boundary restrictions.

Vertical bipolar transistors are added to CMOS processes in order to obtain superior analog and drive capabilities. If these transistors can be isolated, special applications like low-voltage designs for battery-operated circuits or amplifier designs for sensors become possible. We report on a modular 40 V BiCMOS process where junction-isolated vertical npn and pnp transistors have been added for smart-power purposes.

Constructive Solid Geometry (CSG) is a solid modeling technique widely used for the design of semiconductor devices. With the simulation domain subdivision algorithm presented in this paper, the minimal number of solid modeling operations is required in order to build a three-dimensional (3D) device structure. The algorithm is based on a drawing method which combines information on photolithographic masks into a color raster. In this way, solid modeling operations are performed only once on regions having the same color.

Since general-purpose 3D process simulators are currently not available, solid modelers greatly help the designer in building geometries for device simulators. In this contribution, a solid modeler is presented that allows reliable geometrical operations. In order to avoid numerical errors occurring at the intersection of objects built with polygons, we have chosen a data structure based on a discretization of the x-y plane of the simulation domain