Circuit aging simulations face the challenge of correctly accounting for BTI recovery effects in the context of various AC and DC workloads. Many previous studies have shown the cyclical nature of BTI aging with the application of intermittent periods of DC stress. However, scant attention has been paid to the aging behavior for more realistic mission profiles comprised of alternating periods of AC and DC stress. Furthermore, applying the transistor-level understanding of aging behavior for realistic, complex waveforms to a practical simulation approach has not been well addressed in the literature, leading to possible underestimation of circuit-level aging. This work addresses this gap by quantifying transistor aging behavior under realistic conditions, then merges this understanding with circuit-level evaluations, and ultimately concludes that NBTI recovery benefits should not be universally assumed to apply to circuit aging reliability assessments.

This work reports a new mechanism to create highly accelerated hot-carrier damage into FinFET devices by two-photon laser. This method is analogous to real use hot-carrier damage and offers an interesting alternative to understand the aging effects in VLSI circuits for high reliability applications.

The Intel 4 CMOS FinFET technology delivers over 20% performance gains at iso-power over the prior generation (Intel 7). This paper reports reliability studies on the Intel 4 technology that demonstrate matched or better reliability while extending Moore's law in the areas of power, performance, and scaling over its predecessor. Industry-leading technology scaling comes with numerous challenges, including co-optimization of yield, performance, and reliability. This paper reports the development of Intel 4 technology with industry-standard reliability while delivering significant advancement in generational performance and density.

Transistor aging under complex input waveform stress has been a key concern for device and circuit reliability. The overall Design Technology Co-Optimization (DTCO) is strongly guided by the reliability risk of a single transistor as well as by the reliability performance of the overall IP/product. Although the IP/Product reliability evaluation is most beneficial at the early stages of the technology development, it is often very expensive, and no certain aging model methodology exists to quantify the risks. In this work, for the first time we demonstrate a unified aging model framework, which not only can predict the traditional DC transistor aging, but also can accurately predict aging in various styles of circuits. Various Ring-Oscillators (RO) under arbitrary stress conditions are used to demonstrate model predictability after long-term stress approaching product use conditions. Such consistent framework helps to guide the process technology development, as well as provides for high-confidence product/IP reliability design assurance.

The source-drain punch-through current in off-state TDDB stress (OSS) is shown to significantly affect off-state breakdown behavior. This paper compares various OSS methodologies available in the literature and discusses how source-to-drain punch-through affects off-state breakdown and reliability. The proposed Drain-stress with Offset (DSO) OSS methodology limits punch-through to better reflect the actual field dependence of OSS breakdown for scaled tri-gate MOSFET technologies.

Physical Unclonable Functions (PUFs) are low-cost cryptographic primitives used to generate unique, secure, and stable IDs for device authentication and secure communication. PUFs rely on process variation inherent in the manufacturing flow making it impossible to predict or clone chip IDs providing a high level of security and tamper resistance. A commonly studied PUF is the memory PUF which suffers high Bit Error Rate (BER) across environmental conditions. This paper introduces a novel NFET PUF featuring a Hot Carrier Injection (HCI) stress mechanism to lower BER to near zero. Post-Si data from a lkb PUF array fabricated in Intel4 FinFET technology is presented in comparison to a hybrid-SRAM style PUF. BER results were studied with different stress parameters enabling manufacturing flow for HCI based PUFs.

The source-drain punch-through current in off-state TDDB stress (OSS) is shown to significantly affect off-state breakdown behavior. This paper introduces a modified methodology for conducting OSS in scaled tri-gate devices at accelerated conditions that avoids artifacts associated with punch-through while enabling reliability risk assessment. The methodology is validated for both NMOS & PMOS devices and provides consistent degradation mechanism. Finally, it is shown that on-state gate-oxide TDDB remains the reliability limiter compared to OSS TDDB.

Circuit reliability is a significant concern in scaled technologies. Physical aging models derived by DC stress on discrete devices are accurate to an extent, but can be further improved by evaluating the behaviour of simple circuits such as ring oscillators (RO). In this work, we establish correlation between individual device degradation to circuit’s figure of merit (frequency degradation) to refine understanding of the predictive ability of DC models. We further present novel re-configurable circuits that enables different waveform scenarios seen in design to bridge gaps between DC-stressed device aging and complex circuits. Unique features of this work include: (1) Correlating discrete device degradation to circuit performance degradation, (2) development of a novel PMOS/NMOS aging isolator circuit (PNI) which can isolate the aging contribution of a single device type, and (3) development of a state-of-art re-configurable circuit that modulate waveforms to customize the aging contribution from any particular physical mechanism (NBTI, PBTI, N-HCI or P-HCI).

In the Intel reliability stress lab, various transistor testing methodologies are being developed to meet the evolving requirements of new Intel technologies. To better control for voltage drop in metal routing, MOSFETs structures used for reliability tests such as hot carrier injection (HCI) or bias temperature instability (BTI), have evolved from 4 terminals to 6 terminals to enable Kelvin-style testing. In this work, a software-based Kelvin Measurement using Jacobian feedback control theory is developed providing great flexibility on different test structures and optimize use of existing SMU channels. Details are presented for Jacobian Feedback Kelvin Measurements (JFKM) on voltage control, examples of types of test issues, and the measures to improve the convergence of the feedback loop. With a thorough study of JFKM, a high level of data accuracy has been maintained while tool flexibility and throughput have been maximized.

With continuous channel length scaling and ongoing demand for higher operating frequencies, HCI degradation and combining BTI and HCI aging mechanisms in compact aging models becomes important for accurately capturing end-of-life circuit behavior. We have developed an aging playback model that can replay aged transistor I-V characteristics over a large bias range including both mechanisms. The model uses the transistor VT shift, mobility degradation, and a localization coefficient to combine the impact of individual BTI and HCI components. It can be used for both NMOS and PMOS, as well as logic and I/O devices and is part of Intel process design kits.

The 22FFL technology developed for operation to 3.3V is used to investigate process and design considerations required to extend technology capability to 12 V applications. A prototype chip was carefully designed in close consideration with the technology reliability requirements of the lower voltage components to demonstrate product-level reliability capabilities. The reliability of components such as transistors, well junctions, back-end dielectrics and MIMCAPs is thoroughly characterized and proven robust throughout a 10-year lifetime. The results demonstrate a reliable technology capability that is compliant with industrial standards to enable high-voltage design requirements.

We provide a comprehensive overview of the reliability characteristics of Intel’s 10+ logic technology. This is a 10 nm technology featuring the third generation of Intel’s FinFETs, seventh generation of strained silicon, fifth generation of high-k metal gate, multi-Vt options, contact over active gate, single-gate isolation, 14 metal layers, low-k inter-layer dielectric, multi-plate metal-insulator-metal capacitors, two thick-metal routing layers for low-resistance power routing, and lead-free packaging. The technology meets all relevant reliability metrics for certification.

Design-technology co-optimization of Intel's first FinFET Anti-Fuse (AF) memory using 22FFL technology is reported. The nMOS based 1T1C bit cell containing TG and TnG is sized to satisfy electrical performance, process marginality, area, and reliability spec. With gate dielectric breakdown as the mechanism of bit storage, it is found that improved gate oxide integrity is beneficial to post-breakdown resistance and overall array yield. Special attention on well design, source/drain optimization, gate height targeting and array layout in the face of 3-dimentional resistor networks in FinFET can significantly modulate array health. A 2.8 k-bit AF array with baseline yield exceeding 99.9% at no added process cost with medium SA margin setting is demonstrated.

Reliability is an important consideration during semiconductor technology development, which ensures that the performances of devices, circuits, and systems are maintained over a specified period of time, leading to successful products. Device reliability is at the core of overall product reliability, which continues to remain an important area of research and has attracted the attention of IEEE T...

BTI has long been a concern for transistor reliability, and as such garnered significant attention for process optimization and qualification. Typically, the details of a given technology are reported in the literature at the time of qualification. However, not much attention is paid to the larger trends that emerge generation to generation. In this work, we describe the trends when scaling from the 90 nm to 14 nm technology nodes, detail the implications of scaling and architecture changes, as well as discuss the challenges associated with modeling BTI as technologies evolve.

This paper describes the transistor reliability of Intel's 22FFL FinFET technology, which includes an extensive variety of device offerings to enable high performance and low power design options. Detailed evaluations of BTI, TDDB, self-heating, and HCI are included to demonstrate the impact from the various device's pitch, channel length, and threshold voltage. Process integration details are included to highlight the interaction with reliability mechanisms. In addition, modeling results are shown to be well matched to silicon on both discrete devices and benchmark circuits.

Development of an industry leading 10nm CMOS process technology with the highest reported drive currents and cell densities involved numerous enabling innovations, judicious choice of design rules, novel features, and most importantly a relentless pursuit of performance-reliability co-optimization. This paper reports that Intel's 10nm technology achieved scaling benefit over its preceding 14nm generation at matched or better transistor reliability. An elaborate study of the challenges to scaling is presented, which once addressed, enabled meeting aggressive technology reliability targets.

On advanced technology nodes, increases in power density, non-planar architectures and different material systems can exacerbate local self-heating due to active power dissipation, which can affect device performance and reliability in various ways. This paper presents an overview of the research on self-heating in transistors and discusses modulators, measurement schemes, spatio-temporal sensitivities, and impacts on performance and reliability. As the industry continues to scale dimensions and power densities, the significance of self-heating effects will continue to grow, and a robust frame-work to fully assess it, and deal with its impacts to circuits and IP blocks are essential.

The transistor reliability characterization of a 14nm System-on-Chip (SoC) node optimized for low power operation is described. In-depth assessments of reliability and performance for Core and I/O devices are performed on Logic and SoC nodes, and clear trends with scaling are identified. Insight is provided into hot carrier and off-state aging, and self-heat effects. Technological advancements across process nodes demonstrate the ability to achieve matched or improved reliability in conjunction with robust generational performance gains. The 14nm SoC node is shown to be robust for all transistor reliability modes. Process monitor data are used to demonstrate the stability of the production line in high-volume manufacturing.