Recent attention has been given to metal–oxide–semiconductor field-effect transistor (MOSFET) device designs that utilize stress to achieve performance gain in both n-type MOSFETs (NMOS) and p-type MOSFETs (PMOS). The physics behind NMOS gain is better understood than that of PMOS gain, which has received less attention. In this letter, we describe the warping phenomena which is responsible for the gain seen in [110] uniaxially stressed PMOS devices on [100] orientated wafers. We also demonstrate that shear uniaxial stress in PMOS is better suited to MOSFET applications than biaxial stress as it is able to maintain gain at high vertical and lateral fields.

A leading-edge 90-nm technology with 1.2-nm physical gate oxide, 45-nm gate length, strained silicon, NiSi, seven layers of Cu interconnects, and low-/spl kappa/ CDO for high-performance dense logic is presented. Strained silicon is used to increase saturated n-type and p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) drive currents by 10% and 25%, respectively. Using selective epitaxial Si/sub 1-x/Ge/sub x/ in the source and drain regions, longitudinal uniaxial compressive stress is introduced into the p-type MOSEFT to increase hole mobility by >50%. A tensile silicon nitride-capping layer is used to introduce tensile strain into the n-type MOSFET and enhance electron mobility by 20%. Unlike all past strained-Si work, the hole mobility enhancement in this paper is present at large vertical electric fields in nanoscale transistors making this strain technique useful for advanced logic technologies. Furthermore, using piezoresistance coefficients it is shown that significantly less strain (/spl sim/5 /spl times/) is needed for a given PMOS mobility enhancement when applied via longitudinal uniaxial compression versus in-plane biaxial tension using the conventional Si/sub 1-x/Ge/sub x/ substrate approach.