Process and device simulation has been invaluable for logic technology development for many technology nodes. The main goal of this work will be to review the broad and diverse simulation hierarchy that is used in industry to understand and optimize both current and future device technology options. This hierarchy spans both continuum modeling and atomistic methods / beyond continuum tools. Current process and device simulation results will be presented along possible extensions to the hierarchy to improve TCAD’s ability to help technology development.

In the past 25 years, process and device TCAD used in direct support of industrial process development has undergone radical change. In the era of Dennard scaling [1], TCAD efforts in manufacturers such as Intel could arguably be described as advanced applications work. However, with the advent of nanometer device dimensions, the need to calculate fundamental material properties on the fly, resolve quantum effects, and understand the role of atomic-scale defects has shifted TCAD from engineering towards research. Rigorous solutions to Schrodinger’s equations based on NEGF and DFT and semi-classical solutions of the BTE are now in routine use. Concurrently, aging continuum models such as drift-diffusion continue to be infused with more rigorous approaches to maintain accuracy while still affording the fast turn-around-time required by today’s development, which now involves a significant number of novel options under simultaneous consideration. This talk will contrast Intel’s TCAD environment of 25 years ago with today’s and give examples of studies which illustrate the evolution.

Direct bandgap transition engineering using stress, alloying, and quantum confinement is proposed to achieve high performing complementary n and p tunneling field effect transistors (TFETs) based on group IV materials. The critical tensile stress for this transition decreases in Ge1−xSnx for Sn content 0≤x≤0.068, calculated with the Nonlocal Empirical Pseudopotential method. Direct sub eV bandgap leads to high ON current in both n and p Ge and Ge1−xSnx TFETs, simulated using the sp3d5s*-SO model. Ge and Ge1−xSnx show an advantage over III-V p TFETs achieving steep subthreshold operation, which is limited in III-V devices by their low density of electron states.

We review our novel simulation approach to model the effects of applied stress and wafer orientation by mapping detailed dependencies of long channel physics onto short channel device conditions in Silicon NMOS and PMOS. We use kp and Monte Carlo methods to show the long channel dependencies of these effects on gate fields, doping levels, extrinsic charges, and homogeneous driving fields. Our model predicts the reduced effect of wafer orientation on short channel linear and saturation current drives due to weak gate confinement, high carrier density, high stress, and high driving field prevalent in scaled devices. This reduces NMOS (110) wafer orientation loss compared to (100), while keeping PMOS (110) gains over (100) surface orientation in current drives in 〈110〉 channels, consistent with data.

For the first time, the performance impact of (110) silicon substrates on high-k + metal gate strained 45 nm node NMOS and PMOS devices is presented. Record PMOS drive currents of 1.2 mA/um at 1.0 V and 100 nA/um Ioff are reported. It will be demonstrated that 2D short channel effects strongly mitigate the negative impact of (110) substrates on NMOS performance. Narrow width (110) device performance is shown and compared to (100) for the first time. Device reliability is also reported showing no fundamental issue for (110) substrates.

We have developed a novel simulation approach to model electron mobility in the inversion layer which encompasses all the important effects of arbitrary wafer and applied stress orientations, such as carrier re-population, band warping, and scattering, going beyond the separate treatments of band warping and inversion anisotropy that have been demonstrated. Our model predicts an important consequence of electron band warping in retaining the increase of stress gain at high stress levels in the presence of shear stress at strong inversion.

Since the mid-1980's a great deal of effort has gone into simulation of wafer and die-scale thermal behavior during "conventional" rapid thermal processing (RTP) anneals. With ultra-fast anneal processes such as flash-lamp anneal and laser anneal taking a more prominent position in semiconductor manufacturing. The fundamentals of wafer heating such as time scales, associated lengths scales, and the spectral distribution of radiation used are revisited. The authors explore how the ultrafast anneal processes are expected to interact with pattern-scale effects revealing how simulation analysis will be critical component in bringing new radiation anneal processes to manufacturing

We have developed a quantum anisotropic transport model for holes which, for the first time, allows mobility to be studied under both uniaxial and arbitrary stress in PMOS inversion layers. The anisotropic bandstructure of a 2D quantum gas is computed from a 6-band stress dependent k.p Hamiltonian. Our unique momentum-dependent scattering model also captures the anisotropy of scattering. A comprehensive study has been performed for uniaxial stress, biaxial stress, and their nonlinear interactions. The results are compared with device bending data and piezoresistance data, showing very good agreement.

Strained-silicon (Si) is incorporated into a leading edge 90-nm logic technology . Strained-Si increases saturated n-type and p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) drive currents by 10 and 25%, respectively. The process flow consists of selective epitaxial Si/sub 1-x/Ge/sub x/ in the source/drain regions to create longitudinal uniaxial compressive strain in the p-type MOSFET. A tensile Si nitride-capping layer is used to introduce tensile uniaxial strain into the n-type MOSFET and enhance electron mobility. Unlike past strained-Si work: 1) the amount of strain for the n-type and p-type MOSFET can be controlled independently on the same wafer and 2) the hole mobility enhancement in this letter is present at large vertical electric fields, thus, making this flow useful for nanoscale transistors in advanced logic technologies.

Recent attention has been given to metal–oxide–semiconductor field-effect transistor (MOSFET) device designs that utilize stress to achieve performance gain in both n-type MOSFETs (NMOS) and p-type MOSFETs (PMOS). The physics behind NMOS gain is better understood than that of PMOS gain, which has received less attention. In this letter, we describe the warping phenomena which is responsible for the gain seen in [110] uniaxially stressed PMOS devices on [100] orientated wafers. We also demonstrate that shear uniaxial stress in PMOS is better suited to MOSFET applications than biaxial stress as it is able to maintain gain at high vertical and lateral fields.

A leading-edge 90-nm technology with 1.2-nm physical gate oxide, 45-nm gate length, strained silicon, NiSi, seven layers of Cu interconnects, and low-/spl kappa/ CDO for high-performance dense logic is presented. Strained silicon is used to increase saturated n-type and p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) drive currents by 10% and 25%, respectively. Using selective epitaxial Si/sub 1-x/Ge/sub x/ in the source and drain regions, longitudinal uniaxial compressive stress is introduced into the p-type MOSEFT to increase hole mobility by >50%. A tensile silicon nitride-capping layer is used to introduce tensile strain into the n-type MOSFET and enhance electron mobility by 20%. Unlike all past strained-Si work, the hole mobility enhancement in this paper is present at large vertical electric fields in nanoscale transistors making this strain technique useful for advanced logic technologies. Furthermore, using piezoresistance coefficients it is shown that significantly less strain (/spl sim/5 /spl times/) is needed for a given PMOS mobility enhancement when applied via longitudinal uniaxial compression versus in-plane biaxial tension using the conventional Si/sub 1-x/Ge/sub x/ substrate approach.

We describe the device physics of uniaxial strained silicon transistors. Uniaxial strain is more effective, less costly and easier to implement. The highest PMOS drive current to date is reported: 0.72mA/ /spl mu/m. Pattern sensitivity and mobility/Rext partitioning are discussed. Finally we measure inverter delays as low as 4.6pS, and show 50Mb SRAMs operational at 0.65V.

A leading edge 90 nm technology with 1.2 nm physical gate oxide, 50 nm gate length, strained silicon, NiSi, 7 layers of Cu interconnects, and low k carbon-doped oxide (CDO) for high performance dense logic is presented. Strained silicon is used to increase saturated NMOS and PMOS drive currents by 10-20% and mobility by >50%. Aggressive design rules and unlanded contacts offer a 1.0 /spl mu/m/sup 2/ 6-T SRAM cell using 193 nm lithography.

This paper presents a highly-manufacturable process technology featuring SiGe HBT devices fully integrated into a 90 nm leading-edge high performance CMOS technology. The technology was developed on a 300 mm wafer platform, and supports process elements including RF CMOS devices, a MIM capacitor, precision resistors, high-Q inductors and varactors.