This work presents an temperature sensor designed in a 22 nm process, using the 22-FDX design kit for this purpose. This sensor utilizes the threshold voltage and carrier mobility dependence on the temperature for voltage conversion, covering a temperature range of 0 degrees C to 100 degrees C. A key contribution of this work is the exceptionally low error of +0.137 degrees C and -0.075 degrees C achieved after a simulated one-point calibration. In addition, this device achieves a temperature coefficient of -1.69 mV/degrees C in the whole temperature range. It also consumes 23.11 mu A from a 0.8 V DC supply and has an estimated die area of 5024.9 mu m(2) (based on the schematic), of which approximately 5000 mu m(2) correspond to two MOM capacitors. These capacitors are required for stand-alone measurement, but in real-life scenarios, part of this capacitance corresponds to the load capacitance seen when an ADC is connected to the sensor's output. This temperature sensor is suitable for high-accuracy on-chip applications, standing out for its trade-off between area, temperature range, power consumption, error and temperature coefficient.
This paper presents a Deep Learning-based method for fetal and maternal heart rate monitoring, specifically designed for efficient hardware implementation. The proposed approach minimizes computational load by eliminating the denoising and filtering stages. The abdominal electrocardiogram (aECG) signal is thus segmented into 100 ms windows, which are processed by a Convolutional Neural Network (CNN) suitable for real-time implementation on edge devices. This design enables low-latency, continuous heart rate monitoring during pregnancy, supporting fetal well-being assessment and early detection of anomalies. In addition to its suitability for real-time applications, the method can detect fetal arrhythmias, thus providing valuable clinical insights during prenatal care.
This work builds on a recent contribution from the literature to improve isolation on single-pole single-throw switches by introducing an additional transistor at the gate of the series devices in a series-shunt architecture implemented in an FDSOI process. This paper explores the effects of this extra transistor when used in single-pole double-throw switches implemented with RF CMOS transistors in a 130 nm SiGe technology over the 6-20 GHz range. The insights drawn from the post-layout simulations confirm improved isolation, albeit at the cost of higher area consumption, lower output power handling, and higher insertion loss. The overall performance is evaluated using a figure of merit that combines these parameters, showing that the series-shunt configuration offers the best trade-off, while the analyzed approach may be advantageous in applications with area-constrained designs or very high isolation requirements.
This paper presents a system for automatic classification of telecommunication signals using signal processing, multi-domain features fusion, and machine learning techniques. Our system achieves a 97.72% classification accuracy across a wide range of SNR values (-20 dB to 18 dB) using an over-the-air radio-frequency (RF) signals dataset, while maintaining a relatively low complexity (167k learnable parameters). We employ a comprehensive feature extraction methodology that combines time-frequency representations, wavelet transform coefficients, and frequency domain statistics which are processed through a multi-layer architecture. This work demonstrates a systematic approach to signal classification that balances accuracy, computational efficiency, and generalization capability, with potential applications in spectrum monitoring, electronic defense, and cognitive radio systems.
Robust transmission of underwater acoustic signals is essential for the development of Internet of Underwater Things (IoUT) applications such as environmental monitoring, marine exploration, and also for the underwater localization of mobile entities. Underwater localization systems require the emission of pre-coded and modulated acoustic signals, which must be stored in the designed hardware and transmitted with high accuracy and reliability. This work compares two FPGA-based architectural approaches for managing the reading and emission of acoustic encoded signals stored on a microSD card for transmission in underwater environments. On the one hand, a fully hardware implementation by using finite state machines (FSMs) is presented; on the other hand, a soft-core processor to manage SD card access. The comparative analysis of both implementations is focused on performance, resource usage, design complexity, and flexibility. Experimental results show that both solutions are functional for underwater acoustic applications, highlighting advantages and limitations for the design of underwater embedded systems that require robust data handling from microSD memory.
This presents a comprehensive analysis and evaluation of the Improved Modified Zeta Inverter (IMZI), designed to interface photovoltaic systems with the single-phase utility grid. The IMZI topology is constructed using two Zeta converters operating in continuous conduction mode. The IMZI output current is controlled using a quadratic linear regulator. This paper presents the qualitative and quantitative analysis of the IMZI, including the small-signal modeling and control design. A comparative study involving IMZI and other modified Zeta inverter topologies is also conducted. The feasibility and performance of the IMZI are verified through computational simulations. The results demonstrate that the IMZI injects current into the utility grid with low harmonic distortion and achieves a conversion efficiency of 94%.
State-of-the-art safety-critical systems are increasingly integrating advanced functionality that requires high computational power, such as the pedestrian detection required by autonomous vehicles. Consequently, high-performance embedded platforms are becoming increasingly necessary. In this context, the use of Linux is highly attractive to industry due to its extensive ecosystem (platform support, AI libraries, etc.) and its opensource development model. However, Linux was not designed to comply with strict safety standards, which complicates its use in safety-critical systems. Previous works have studied the nondeterminism of Linux kernel system calls regarding their execution paths and execution times, and proposed alternative approaches to justify its use in such systems. In this work, we continue those efforts with two main contributions. First, we compare a regular Linux kernel with the kernel patched with the PREEMPT_RT real-time patch, and show how the patch reduces the variability of system calls, both in terms of timings and execution paths. Then, we propose an additional layer of assurance in the form of a trie-based monitor implemented in hardware, which ensures that the variability measured and estimated during testing holds when the system is fielded, both for execution paths and execution times. We implement a software prototype of the monitor to demonstrate its feasibility and discuss our plan to migrate it to hardware.
Determining movement intention in patients with partial spinal cord injury or stroke remains challenging, requiring efficient frameworks to decode muscle activity for assistive and rehabilitation technologies. Surface electromyography (sEMG) provides a non-invasive way to monitor muscle activation, but its analysis is affected by noise and the complexity of extracting discriminative features for robust classification. This work proposes a complete pipeline for sEMG feature extraction and lower-limb movement classification using a multilayer perceptron (MLP) implemented on an FPGA-based System-on-Chip (SoC). sEMG signals from eight muscles were processed to distinguish sitting, standing up, remaining still, and walking. Four computationally efficient time-domain features-Average Power (AP), Mean Absolute Value (MAV), Integrated sEMG (IEMG), and Simple Squared Integration (SSI)-were extracted and fed into the network. The system achieved 92.5% accuracy and sub-millisecond inference latency, demonstrating a practical trade-off between accuracy, latency, and hardware efficiency. Unlike most state-of-the-art approaches that rely on offline GPU processing, our design enables real-time operation on a compact, low-power SoC platform. These results confirm the feasibility of deploying machine learning models for portable rehabilitation devices, paving the way for intelligent, resource-efficient human-machine interfaces in clinical environments.
In this paper, an improved discrete-time potentiostat architecture is proposed. The focus is placed on the digital controller, aiming to enhance its performances, reduce measurement uncertainty and increase speed. The system is modeled including its non-linear behavior, and the impact of the digital controller parameters on the system response is analyzed through behavioral simulations. The developed mathematical model shows good agreement with the simulation results. The new controller successfully reduces the measurement uncertainty compared to a purely integral control system by up to a factor of 100 in the worst-case scenario. The system speed is also improved by approximately 40%. The new digital controller not only improves the overall performance of the system, but also does not increase significantly the hardware complexity of the system.
This work presents the design and post-layout simulation of a cryogenic SiGe BiCMOS low-noise amplifier (LNA) for superconducting transmon-qubit readout in quantum processors scaling beyond hundreds of qubits. The target specifications are first established and justified by surveying state-of-the-art of cryogenic LNAs and modeling the dispersive qubit readout process. The LNA is implemented with three cascaded stages in common-emitter configuration and employs tuned inductive matching and parallel peaking networks in each stage to optimize noise, gain flatness, and bandwidth while maintaining minimal DC power consumption. The amplifier draws only 1.15 mW from a 0.15 V supply and occupies 0.252 mm(2). Post-layout simulations confirm input/output S-parameter matching better than -10 dB, 41-44 dB gain with <3 dB ripple, <5 K noise temperature across 4-9 GHz, and a worst-case OP1 dB compression point of -19.96.6 dBm. A comparative analysis demonstrates that SiGe BiCMOS offers a favorable trade-off between InP HEMT's low noise and CMOS's integration potential for large-scale quantum processors.
A fully-differential CMOS current-mode Sinh companding second order low pass filter is presented. The main advantages of the proposed filter are low supply voltage requirements, low static power consumption and large frequency tuning range. Measurement results of a test chip prototype are presented, showing a frequency tuning range spanning from 50kHz up to 2MHz. For 1.2MHz bandwidth, the circuit achieves a dynamic range of 99.7dB and a power consumption of 45 mu W using a supply voltage of 1.5V. The silicon area of the fabricated filter is 0.256mm(2).
Biometric-as-a-Service (BaaS) recognition systems have gained widespread adoption across several sectors due to their advantages in terms of cost-efficiency, scalability and performance. In these systems, the raw fingerprint images collected by sensors are transmitted to remote nodes through secure channels. The nodes often use SoC-FPGAs to accelerate processing with hardware. Also, they incorporate advanced security measures. However, they are not very concerned about possible side-channel attacks that can retrieve biometric data at operation level. To raise awareness of this problem, this paper presents an electromagnetic (EM) side-channel attack at a PYNQ Z1 board. It is performed while the SoC-FPGA is reading the fingerprint image from the DDR3 memory. Fuzzy-logic-based rules are extracted during a training phase to explain the correlation between the electromagnetic emanations measured and the pixels transmitted. With that rule base, the attacker needs only one EM trace, acquired in 69.10.s or less in our experiments, to reconstruct the fingerprint image, reaching pixel-wise accuracy of 99.05%.
This work presents a sub-nanowatt Wake-Up Timer for energy-harvesting IoT applications, based on a thyristor-based ring oscillator and asynchronous digital logic. Fabricated in 180 nm CMOS, the circuit has a power consumption of (100 +/- 55) pW at 1.2 V with a oscillation frequency of (0.40 +/- 0.07) Hz. It includes a programmable prescaler and a 19-bit counter, enabling long sampling intervals with minimal area (compared to other solutions such as Wake-Up Receivers). The design demonstrates stable operation across multiple samples and extended testing, offering a compact and energy-efficient solution for ultra-low duty cycle sensing nodes.
A capacitor-less low-dropout (LDO) regulator with nanosecond-transient response for modern smart edge AI processors is presented. The LDO employs an operational transconductance amplifier (OTA) as the error amplifier and an inverter-based amplifier that provides a high DC gain. The proposed LDO was designed in 65-nm complementary metal oxide semiconductor (CMOS), allowing for an output range of 0.4-1.6 V from an 1.8 V input and a maximum 300 mA load current. The simulated output undershoot is 60 mV with a load current step from 10 to 300 mA and a 20 ns edge-time. The proposed LDO consumes 243 mu A and has a transient response time of 9.97 ns with steps of 10 to 300 mA and 37.2 ns with steps of 300 to 10 mA.
In this article, we present a lightweight peripheral of the Advanced Encryption Standard (AES) algorithm suitable for its implementation as a memory mapped peripheral in RISC-V cores. The peripheral is based on an 8-bit serial implementation of AES, which achieves a drastic reduction in the time required to encrypt a message with a reduced increase in resource consumption. The peripheral is compared in terms of resource utilization and timing with a software implementation of AES, tinyAES-c, and a hardware implementation that employs a more common 128-bit datapath using the Series-7 FPGA technology of the manufacturer AMD-Xilinx. The results show that the system using the peripheral achieves a speed 71.84 times faster than the software implementation, with a 46.37% increase over the logic used to implement the RISC-V processor.
With the rapid growth of Internet of Things (IoT), the demand for Ultra-Low Power (ULP) circuits increased, making power management circuits a critical need. In this context, Fully Depleted Silicon on Insulator (FD-SOI) technology is indicated thanks to an enhanced body biasing possibility's. An Adaptive Body-Biasing (ABB) circuit is therefore needed and must meet the ULP constraints. To address this challenge, a programmable negative sampling solution optimized for ABB circuit in 18 nm FD-SOI technology is proposed. The sampling rate ranges from 10 kHz to 100 MHz and introduces specific design techniques to enhance power consumption and area efficiency. The circuit is composed of a modified 6-bit binary-weighted Capacitive Digital to Analog Converter (CDAC) coupled with a dynamic comparator. This solution exhibits only dynamic power consumption, making it a suitable solution for frequency regulation of the ABB circuit. This implementation can achieve a power reduction up to x460 at 10 kHz and a silicon area reduction by x7.5 compared to a previously implemented design that relies on statically biased functions in the same technology.
This work proposes to utilize a dynamic threshold-voltage MOSFET (DTMOS) technique for Schmitt-Trigger-based circuits that significantly enhances the Ion/Ioff ratio while improving robustness against process variations and mismatch. We designed and validated DTMOS Schmitt Trigger (DST) inverter and NAND gates in a commercial 130nm SOI CMOS technology. Comprehensive post-layout simulations compared noise margins, power dissipation and propagation delay against standard Schmitt-Trigger implementations. Monte Carlo analysis demonstrates that our proposed circuits achieve 99.9% yield at an ultra-low supply voltage of 60 mV. Evaluation of 11-stage inverter- and NAND-based ring oscillators revealed that the DST-based circuits deliver 24-27% improved energy efficiency and 30-37% reduced delay at 90 mV operation, with only a small area overhead. Furthermore, the minimum operating voltage is reduced by 12.5%, with the DST inverter demonstrating functionality at voltages as low as 40 mV.
Developing distributed High Performance Computing (HPC) applications is challenging, with complex interactions between application, runtime environment, processing cores, and network to obtain the highest performance that a given distributed computing system can provide. HPC systems are evolving at a fast pace, so applications must often be ported. Generally, developers natively run their applications on current machines and extrapolate the performances on future ones. However, modern and future HPC machines contain multiple nodes, each with multiple general-purpose processor cores, possibly with an Instruction Set Architecture (ISA) different from the previous generations, as well as new domain-specific accelerators, so simple extrapolations may not be accurate. Instead, we propose an automated approach to execute and non-intrusively characterize distributed HPC applications on a QEMU-based, cross-ISA, distributed simulation platform. As part of this automated approach, we propose a QEMU plugin to extract metrics at run-time during the execution of distributed applications. The approach is demonstrated on a RISC-V-based distributed multi-node architecture. It achieves an average speedup of almost 3.5 x on a single host machine with 16 virtual nodes in comparison with a single node. Using QEMU plugins for collecting Message Passing Interface (MPI) runtime metrics slows the simulation by 1.62 x in average, but overall, our approach remains much faster than other simulation platforms.
One of the main features that are expected for 6G networks will be their ability to have a three-dimensional (3D) extension. In contrast with current communications networks, in which the transimission of the signals is carried out at the surface level, this will allow true global coverage including oceans and vast unpopulated areas. 3D global coverage has become a strategic goal and efforts are being put into its implementation with the current deployment of 5G networks and in satellite communications (SATCOM). This requires minimizing the energy losses experienced by electromagnetic waves in the GHz bands. To achieve this goal, the most promising solution is the use of active antenna arrays incorporating smart beamforming techniques to achieve directionality in signal transmission. This work presents the design and simulation of the transmitter path of an active antenna array operating within the European downlink frequency band for SATCOM on the move (SOTM) applications (17.7 to 21.2 GHz). It incorporates a compact phase shifter based on a vector-sum architecture and a power amplifier based on the concatenation of neutralized differential common-source pairs. The transmitter has been designed in a 65nm CMOS MM/RF process. It achieves a phase resolution of 11.25 degrees over the 360 degrees range, with a gain of approximately 22.5 dB using a 5-bit control word while consuming 30mW.
This work presents a comparative study of the Full Adders (FAs) implemented using DTMOS Schmitt-Trigger (DST) standard cells in 130nm SOI CMOS technology, targeting ultra-low supply voltages below 100mV. Multiple DST-based FA topologies were designed and evaluated through extensive post-layout Monte Carlo simulations to assess robustness under process, voltage, and temperature (PVT) variations and device mismatch. Performance metrics, including energy, delay, power, and energy-delay product, were analyzed across a voltage range. The results indicate that the NAND-only FA achieves the highest yield, lowest delay, smallest area, and superior energy efficiency among DST designs. Furthermore, a comparison with a Schmitt-Trigger NAND-only FA shows that the DST NAND-only FA offers greater robustness and improved energy efficiency. The minimum energy point (MEP) of the DST-based FA ring oscillator is 140mV, compared to 170mV for its ST counterpart.
