The paper presents a 16Gb SDRAM with a vertical-channel-transistor-based 4F(2) cell and cell-on-peripheral (COP) architecture. Wafer-to-wafer hybrid copper bonding is applied to COP, which increases the total die count per wafer by more than 20% with the same design rules. Fabricated in a 10nm-class DRAM process, the test chip performs read and write operations successfully, opening the possibility for further DRAM-technology scaling.
We present a 65nm digital Ising chip with an advanced column-bipartite topology, featuring densely connected spins with a degree of 56 and 8b coefficients for mapping and solving computationally intensive combinatorial optimization problems. A fabricated Ising test chip with 64 spin processing elements with spin coefficients stored in flexible embedded SRAM demonstrates solving practical problems, such as MIMO detection for a wireless network, with a fast solution time (< 72ns).
Conventional management of type-1 diabetes (T1D) relies on finger-prick blood sampling or electrochemical methods, which prevent continuous monitoring and treatment. This paper presents a novel epidermal pasting bioelectronic device (PBD). The device integrates a 19fA-resolution bioluminescence analog front-end (BAFE) with TDM-SAR calibration and a hybrid-mode LED driver. It enables closed-loop realtime detection and precision treatment for T1D. The battery life reaches 48 days.
This paper presents a single-transformer multi-output isolated DC-DC converter generating three regulated rails $(+15 ~\mathrm{V},-5 ~\mathrm{V}$, and +5 V) from wide $12 / 24 ~\mathrm{V}$ inputs. By sharing a common secondary winding in a dual-doubler rectifier configuration, the design achieves three outputs using only four power transistors. Additionally, a reconfigurable two-mode inverter ensures high efficiency across both input voltage conditions. The converter reaches a peak efficiency of 68% with maximum output power of 2.5W.
This paper presents edge-triggered transceivers (ETT), enabling a 32Gb UCle-like chiplet interconnect when integrated within an active local silicon interconnect (aLSI). The ETT achieves power consumption of 0.07pJ/b and supports compact top-die TX/RX designs while optimizing 0.36pJ/b energy efficiency and 12.35Tb/s/mm2 area bandwidth density. It demonstrates a 32Gb/s die-to-die link at 0.75V with 20.46ps eye width (65% UI) and 530mV eye height across 64 lanes in a 3nm CMOS process.
